參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 21/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 13
Version 0.93
3.3.3 Extra Long EEPROM Load
An Extra Long Load mode is provided in the PCI 9080
to load 5 more Lwords from the EEPROM. If bit 25 is set
to 1 in the “Local Bus Region Descriptor [LOC 98h]”, the
following 5 Lword registers are loaded in addition to
normal Long Load process (refer to Section 3.3.2).
Bit 25 of the “Local Bus Region Descriptor [LOC 98h]”
must be set to 1 during Long Load Process. (Refer to
Table 3-3.)
Table 3-3. Extra Long EEPROM Load Registers
EEPROM
Offset
EEPROM
Value
Description
44
9080
Subsystem ID
46
10B5
Subsystem Vendor ID
48
FFf0
MSW of Range for PCI to Local Address
Space 1 (1 MB)
4A
0000
LSW of Range for PCI to Local Address
Space 1 (1 MB)
4C
1000
MSW of Local Base Address (Remap)
for PCI to Local Address Space 1
4E
0001
LSW of Local Base Address (Remap) for
PCI to Local Address Space 1
50
0000
MSW of Bus Region Descriptors
(Space 1) for PCI to Local Accesses
52
05C3
LSW of Bus Region Descriptors
(Space 1) for PCI to Local Accesses
54
0000
MSW of PCI Base Address for local
expansion ROM
56
0000
LSW of PCI Base Address for local
expansion ROM
Note: There are 40 unused bytes in the EEPROM that
can be used for user-defined applications.
3.3.4 Recommended EEPROMs
A 1K bit (National NM93CS46 or compatible) or 2K bit
(National NM93CS56 or compatible) device can be
used. Refer to Table 5-2 in Section 5, “Pin Description,”
for EEPROM control pin descriptions.
3.4 INTERNAL REGISTER ACCESS
The PCI 9080 chip provides several internal registers,
allowing for maximum flexibility in bus interface design
and performance. The register types are accessible
from both the PCI and local buses, including the
following:
PCI Configuration Registers
Local Configuration Registers
Mailbox Registers
Doorbell Registers
DMA Registers
Messaging Queue Registers (I
2
O)
Figure 3-1 illustrates how these registers are accessed.
Set
Clear
Local
Bus
Master
PCI
Bus
Master
Local Configuration
Registers
PCI Configuration
Registers
DMA Registers
PCI 9080
Mailbox Registers
PCI to Local
Doorbell Register
Local to PCI
Doorbell Register
Messaging
Queue Registers
Set
Clear
P
L
Figure 3-1. PCI 9080 Internal Register Access
3.4.1 PCI Bus Access to Internal Registers
The PCI 9080 "PCI configuration registers" can be
accessed from the PCI bus with a configuration Type 0
cycle.
The PCI 9080 internal registers can be accessed by a
memory cycle, with the PCI bus address that matches
the base address specified in the PCI Base Address 0
for Memory Mapped Configuration Register of the PCI
9080. They can also be accessed by an I/O cycle, with
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