參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁(yè)數(shù)： 31/133頁(yè)
文件大?。?/td> 883K
代理商： PLI9080
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 23
Version 0.93
3.6 DMA OPERATION
The PCI 9080 supports two independent DMA channels
capable of transferring data from the local bus to the
PCI bus or from the PCI bus to the local bus. Each
channel consists of a DMA controller and a bi-directional
FIFO. Both channels support chaining and non-chaining
transfers, Demand Mode DMA, and End of Transfer
(EOT) pins.
3.6.1 Non-Chaining Mode DMA
The host processor or the local processor sets the local
address, PCI address, transfer count and transfer
direction. The host or local processor then sets a
control bit to initiate the transfer. The PCI 9080 will
arbitrate the PCI and local buses and transfer data.
Once the transfer is complete, the PCI 9080 generates
an interrupt either to the local processor or the PCI host
(programmable). The DMA done bit in the internal DMA
register can be pooled to indicate the status of DMA
transfer.
DMA registers are accessible from the PCI bus and local
bus. (Refer to Figure 3-7.)
PCI Host
Memory
Memory Block
to Transfer
Memory Block
to Transfer
Local
Memory
Mode Register
PCI Address Register
Local Address Register
Transfer Size (byte count) Register
Descriptor Pointer Register
(set direction only)
Command/Status Register
Set DMA Mode
to Non-Chaining
Set up Transfer
Parameters
Set the Enable and
Go bits in the DMA
Command/Status Register
to Initiate DMA Transfer
Figure 3-7. Non-Chaining DMA Initialization
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