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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 78/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 70
Version 0.93
4.5.12 (CNTRL; PCI:6Ch, LOC:ECh) EEPROM Control, PCI Command Codes, User I/O Control,
Init Control Register
Table 4-59. (CNTRL; PCI:6Ch, LOC:ECh) EEPROM Control, PCI Command Codes, User I/O Control, Init Control
Register
Field
Description
Read
Write
Value after Reset
3:0
PCI Read Command Code for DMA. This PCI command is sent out during DMA read
cycles.
Yes
Yes
1110
7:4
PCI Write Command Code for DMA. This PCI command is sent out during DMA write
cycles.
Yes
Yes
0111
11:8
PCI Memory Read Command Code for Direct Master. This PCI command is sent out
during Direct Master read cycles.
Yes
Yes
0110
15:12
PCI Memory Write Command Code for Direct Master. This PCI command is sent out
during Direct Master write cycles.
Yes
Yes
0111
16
General Purpose Output. A value of 1 causes the USERO output to go high. A value
of 0 causes the output to go low.
Yes
Yes
1
17
General Purpose Input. A value of 1 indicates the USERI input pin is high. A value of 0
indicates the USERI pin is low.
Yes
No
—
23:18
Reserved.
Yes
No
0
24
EEPROM Clock for Local or PCI Bus Reads or Writes to EEPROM. Toggling this bit
generates an EEPROM clock. (Refer to the manufacturer’s data sheet for the
particular EEPROM being used.)
Yes
Yes
0
25
EEPROM Chip Select. For local or PCI bus reads or writes to EEPROM, setting
this bit to 1 provides the EEPROM chip select.
Yes
Yes
0
26
Write Bit to EEPROM. For writes, this output bit is the input to the EEPROM.
It is clocked into the EEPROM by the EEPROM clock.
Yes
Yes
0
27
Read EEPROM Data Bit. For reads, this input bit is the output of the EEPROM.
It is clocked out of the EEPROM by the EEPROM clock.
Yes
No
—
28
EEPROM Present. A value of 1 indicates an EEPROM is present.
Yes
No
0
29
Reload Configuration Registers. When this bit is set to 0, writing a 1 causes the PCI
9080 to reload the PCI configuration registers from EEPROM.
Yes
Yes
0
30
PCI Adapter Software Reset. A value of 1 written to this bit holds the local bus logic in
the PCI 9080 reset and LRESETo# asserted. The contents of the PCI configuration
registers and Shared Run Time registers will not be reset. Software Reset can only be
cleared from the PCI bus. (Local bus remains reset until this bit is cleared.)
Yes
Yes
0
31
Local Init Status. A value of 1 indicates local init done. Responses to PCI accesses are
RETRYs until this bit is set. While input pin NB# is asserted low, this bit is forced to 1.
Yes
Yes
0
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