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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 24/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 3
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 16
Version 0.93
3.5.1.5 I/O
If the Configuration Enable bit is clear, a single I/O
access is made to the PCI bus. The local address,
remapped decode address bits and the local byte
enables are encoded to provide the address and is
output with an I/O read or write command during the PCI
address cycle.
For writes, data is loaded into the write FIFO and
READYo# returned to the Local bus. For reads, the PCI
9080 holds off READYo# while gathering a Lword from
the PCI bus.
3.5.1.6 CFG (PCI Configuration Type 0 or
Type 1 Cycles)
If the Configuration Enable bit is set, a CFG access is
made to the PCI bus. In addition to enabling the
configuration (bit 31) of (PCI [2Ch])(Loc [ACh]), the user
must provide all the register information. The register
number (bit [7:2]) or the device number (bit [15:11])
must be modified and a new CFT read/write cycle must
be performed before other registers or devices can be
accessed.
If the PCI Configuration Address Register selects a
Type 0 command, bits [10:0] from the register are
copied to address bits [10:0]. Bits [15:11] “device
number” are translated into a single bit being set in PCI
address bits [31:11]. PCI address bits [31:11] can be
used
as
a
device
command, bits [23:0] are copied from the register
to bits [23:0]
of
the
address bits [31:24] are 0. A configuration read or write
command code is output with the address during the
PCI address cycle.
select.
For
a
Type 1
PCI
address.
PCI
For writes, local data is loaded into the write FIFO and
READYo# is returned. For reads, the PCI 9080 holds off
READYo# while gathering an Lword from the PCI bus.
3.5.1.7 Direct Bus Master Lock
The PCI 9080 supports direct local to PCI bus exclusive
accesses (locked atomic operations). A locked operation
must start with the local bus input LLOCK# being
asserted during a Direct Master bus read cycle. Refer to
the timing in Section 8, “
Timing Diagrams
.” Locked
operations are enabled or disabled using the PCI Base
Address for Direct Master to PCI Register.
3.5.1.8 Master/Target Abort
The PCI 9080 Master/Target abort logic enables a local
bus master to perform a Direct Master bus poll of
devices to determine whether the devices exist (typically
when the local bus performs configuration cycles to the
PCI bus).
If a PCI Master, Target Abort, or Retry Time-out is
encountered during a transfer, the PCI 9080 asserts
LSERR# (can be used as a NMI). If the local bus master
is waiting for a READYo#, it is asserted along with
BTERMo#. The local master’s interrupt handler can take
the appropriate application specific action. It can then
clear the abort bits in the PCI Status Register of the PCI
9080 to clear the LSERR# interrupt and re-enable Direct
Master transfers.
If a local bus master is attempting a burst read from a
non-responding PCI device (Master/Target abort), it
receives the READYo# and BTERMo# for the first cycle
only. If the local processor cannot terminate its burst
cycle, it may cause the local processor to hang. The
local bus must then be reset from the PCI bus or by a
local watch-dog timer asserting RESETi#. If the local
bus master cannot terminate its cycle with BTERMo#, it
should not perform burst cycles when attempting to
determine if a PCI device exists.
3.5.1.9 Write and Invalidate
The PCI 9080 can be programmed to perform Direct
Master write and invalidate cycles through the PCI Base
Address (Remap) Register and the Command Code
Register. In Write and Invalidate mode, the PCI 9080
waits until the local bus writes 8 Lwords before starting
the PCI access. This ensures that an 8 Lword write
completes in one PCI bus ownership, as required for
write and invalidate to a target with a cache line size of
8 Lwords.
Note: Before the write and invalidate cycle, the
command code for Direct Master must be modified to
0Fh at (PCI [6Ch])(Loc [ECh]) and the cache line size at
(PCI [0Ch])(Loc [0Ch]) must match the target cache line
size.
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