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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 26/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 18
Version 0.93
3.5.2
Direct Slave Operation (PCI Master to
Local Bus Access)
The PCI 9080 supports both memory mapped burst
transfer accesses and I/O mapped single transfer
accesses to the local bus from the PCI bus. PCI Base
Address registers are provided to set up the location of
the adapter in PCI memory and I/O space. In addition,
local mapping registers allow address translation from
PCI address space to local address space. There are
three spaces available:
Space 0
Space 1
Expansion ROM space
The Expansion ROM space is intended to support a
bootable ROM device for the host. Each local space
can be programmed to operate 8 bit, 16 bit, or 32 bit
local bus width. The PCI 9080 has an internal wait state
generator and external wait state input (READYi#).
READYi# can be disabled or enabled with the internal
configuration register. The local bus, independent of the
PCI bus, can
Burst as long as the data is available (Continuous
Burst Mode)
Burst 4 Lwords at a time
Perform continuous single cycle, with or without wait
state(s)
For single cycle Direct Slave reads, the PCI 9080 reads
a single local bus Lword or partial Lword. The PCI 9080
disconnects after one transfer for all Direct Slave I/O
accesses.
For the highest data transfer rate, the PCI 9080 supports
posted write and can be programmed to prefetch data
during PCI Burst Read. The prefetch size, when
enabled, can be 1 to 16 Lwords, or until the PCI stops
requesting. The PCI 9080 will prefetch if enabled and
drop the local bus after the prefetch counter is reached.
In a continuous prefetch mode, the PCI 9080 prefetches
as long as any FIFO space is available and terminates
the prefetch when the PCI terminates the request. If
read prefetching is disabled, the PCI 9080 disconnects
after one read transfer.
If the local side is extremely slow, the PCI 9080 can be
programmed through the Local Arbitration and PCI
Mode register to perform delayed reads, as specified in
PCI specification rev 2.1. In addition to delayed read,
the PCI 9080 supports the following in PCI specification
rev 2.1 features.
No write while read is pending(RETRY for reads)
Write and flush pending read
The PCI 9080 also supports cached read mode, where
prefetched data can be read from the PCI 9080 internal
FIFO instead of from the local side. The address must
be subsequent to the previous address and must be 32-
bit aligned (next address = current address + 4).
The PCI 9080 can be programmed to keep the PCI bus
by generating a wait state(s), de-asserting TRDY#, if the
write FIFO becomes full. The PCI 9080 can also be
programmed to keep the local bus, LHOLD is asserted,
if the Direct Slave Write FIFO becomes empty or the
Direct Slave Read FIFO becomes full. The local bus is
dropped in either case when the Local Bus Latency
Timer is enabled and expires.
The PCI 9080 supports on-the-fly Endian conversion for
Space 0, Space 1, and expansion ROM space. The
local bus can be Big/Little Endian by either using the
BIGEND# input pin or the programmable internal
register configuration. When BIGEND# is asserted, it
overwrites the internal register configuration.
Note: The PCI bus is always Little Endian.
3.5.2.1
PCI to Local Address Mapping
Three local address spaces—Space 0, Space 1, and
expansion ROM—are accessible from the PCI bus.
Each space is defined by a set of three registers:
Local Address Range
Local Base Address
PCI Base Address
A fourth register, Bus Region Descriptors for PCI to
Local Accesses Register, defines the local bus
characteristics for both regions. (Refer to Figure 3-6.)
3.5.2.1.1 Byte Enables
LBE[3:0]# (pins 139, 140, 141, and 142) are encoded
based on the configured bus width, as follows:
32-Bit Bus—
For a 32-bit bus, the four byte enables
indicate which of the four bytes are active during a data
cycle.
BE3# Byte Enable 3—LD[31:24]
BE2# Byte Enable 2—LD[23:16]
BE1# Byte Enable 1—LD[15:8]
BE0# Byte Enable 0—LD[7:0]
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