- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368046 > PLI9080 (Electronic Theatre Controls, Inc.) PCI I/O ACCELERATOR PDF資料下載
參數(shù)資料
| 型號(hào)： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 35/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 27
Version 0.93
3.6.6 DMA Arbitration
The PCI 9080 DMA controller releases control of the
local bus (de-asserts LHOLD) when one of the following
occurs:
Its FIFOs are full in a local to PCI transfer
Its FIFOs are empty in a PCI to local transfer
The Local Bus Latency Timer expires (if enabled)
The BREQ input is asserted (BREQ can be enabled
or disabled, or gated with a latency timer before the
PCI 9080 gives up the local bus)
A Direct Slave access is pending
EOT input is received (if enabled)
The DMA controller releases control of the PCI bus
when one of the following occurs:
The FIFOs are full or empty
When the PCI Latency Timer expires and it loses
the PCI grant signal
It receives a Target Disconnect response
It de-asserts its PCI bus request (REQ#) for a minimum
of two PCI clocks.
3.6.6.1 End of Transfer (EOT0# or EOT1#)
Input
When asserted, current DMA transfer terminates,
regardless of the transfer size. Local transfers will
terminate after the current cycle. PCI transfer will
terminate immediately if transfer is from PCI to local. If
the transfer is from local to PCI, the PCI 9080 finishes
transferring all data in the internal FIFO and terminates
the DMA transfer
3.6.6.2 Local Latency and Pause Timers
A Local Bus Latency Timer and Local Bus Pause Timer
are programmable with the DMA Arbitration Register. If
the local latency timer expires, the PCI 9080 completes
the current Lword transfer and releases LHOLD. After its
programmable Pause Timer expires, it reasserts
LHOLD. When it receives LHOLDA, it continues the
transfer. The
PCI bus transfer continues until the FIFO is empty for a
local to PCI transfer or until it is full for a PCI to local
transfer.
3.7 BREQ INPUT
When the PCI 9080 owns the local bus, both its LHOLD
output and LHOLDA input are asserted. When the PCI
9080 samples BREQ asserted during a DMA transfer or
a Direct Slave write transfer, it gives up the local bus
within two Lword transfers by de-asserting LHOLD and
floating its local bus outputs if BREQ is gated or
disabled, or if gating is enabled and the Local Bus
Latency Timer expires. The Local Arbiter can now grant
the local bus to another local master. After the PCI 9080
samples that its LHOLDA is de-asserted and its local
pause timer is zero, it re-asserts LHOLD to request the
local bus. When the PCI 9080 receives LHOLDA, it
drives the bus and continues from where it left off.
3.8 DOORBELL REGISTERS
There are two 32 bit doorbell interrupt/status registers in
the PCI 9080. One is assigned to the PCI bus interface
and while the other is assigned to the local bus
interface.
The local processor can generate a PCI bus interrupt by
writing any number other than all zeroes to the PCI to
local doorbell register.
A PCI host can generate a local bus interrupt by writing
any number other than all zeroes to the local to PCI
doorbell register.
3.9 MAILBOX REGISTERS
There are eight 32 bit mailbox registers in the PCI 9080
that can be written to and read from both buses. These
registers can be used to pass command and status
information directly between local and PCI bus devices.
A local interrupt can be generated, if enabled, when the
PCI host writes to one of the first four mailbox registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PLL0210A | PHASE LOCKED LOOP |
| PLL0210A | PHASE LOCKED LOOP |
| PLL0305A | Serial-Input Frequency Synthesizer |
| PLL1045A | Phase-Locked Loop |
| PLL1070A | PHASE LOCKED LOOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PLI-A10 | 制造商:Banner Engineering 功能描述:Plastic Fiber Convergent, Core Dia.: 0.5 mm & 9 x 0.25 mm, Fiber Length 2 m, Le |
| PLIC/DUSB_PHY/AA | 制造商:PLDA 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature) |
| PLIC/DUSB_PHY/XX | 制造商:PLD Applications Inc 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature) 制造商:PLDA 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature) |
| PLIC/EZDMA/X8/GEN1/XX | 制造商:PLD Applications Inc 功能描述:PERMANENT ENCRYPTED LICENSE FOR A X1/X4/X8 PCIE EZDMA IP - Virtual or Non-Physical Inventory (Software & Literature) |
| PLIC/LITE/X8/GEN1/XX | 制造商:PLD Applications Inc 功能描述:PERMANENT ENCRYPTED LICENSE FOR A X1/X4/X8 PCI EXPRESS IP C - Virtual or Non-Physical Inventory (Software & Literature) |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。