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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 71/133頁 |
| 文件大小： | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 63
Version 0.93
4.4.11 (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to
PCI Memory
Table 4-43. (DMPBAM; PCI:28h, LOC:A8h) PCI Base Address (Remap) Register for Direct Master to PCI Memory
Field
Description
Read
Write
Value after Reset
0
Direct Master Memory Access Enable. A value of 1 enables decode of Direct Master
Memory accesses. A value of 0 disables decode of Direct Master Memory accesses.
Yes
Yes
0
1
Direct Master I/O Access Enable. A value of 1 enables decode of Direct Master I/O
accesses. A value of 0 disables decode of Direct Master I/O accesses.
Yes
Yes
0
2
LLOCK# Input Enable. A value of 1 enables LLOCK# input, enabling PCI-locked
sequences. A value of 0 disables the LLOCK# input.
Yes
Yes
0
12, 3
Direct Master Read Prefetch Size control. Values:
00 = The PCI 9080 continues to prefetch read data from the PCI bus until the Direct
Master access is finished. This may result in an additional 4 unneeded Lwords being
prefetched from the PCI bus.
01 = Prefetch up to 4 Lwords from the PCI bus
10 = Prefetch up to 8 Lwords from the PCI bus
11 = Prefetch up to 16 Lwords from the PCI bus
If PCI memory prefetch is not wanted, performs a Direct Master single cycle.
The direct master burst reads must not exceed the programmed limit.
Yes
Yes
00
4
Direct Master PCI Read Mode. A value of 0 indicates the PCI 9080 should release the
PCI bus when the read FIFO becomes full. A value of 1 indicates the PCI 9080 should
keep the PCI bus and de-assert IRDY when the read FIFO becomes full.
Yes
Yes
0
10, 8:5
Programmable Almost Full Flag. When the number of entries in the 32 word direct
master write FIFO exceeds this value, the output pin DMPAF# is asserted low.
Yes
Yes
000
9
Write and Invalidate Mode. When set to 1, the PCI 9080 waits for 8 or 16 Lwords to be
written from the local bus before starting PCI access. When set, all local Direct Master
to PCI write accesses must be 8 or 16 Lword bursts.
Yes
Yes
0
11
Direct Master Prefetch Limit. If set to 1, don’t prefetch past 4 K (4098 bytes)
boundaries.
Yes
Yes
0
13
I/O Remap Select. When set to 1, forces PCI address bits [31:16] to all zeros.
When set to 0, uses bits [31:16] of this register as PCI address bits [31:16].
Yes
Yes
0
15:14
Direct Master Write Delay. This register is used to delay the PCI bus request after
direct master burst write cycle has started. Values:
00 = no delay; start the cycle immediately
01 = delay 4 PCI clocks
10 = delay 8 PCI clocks
11 = delay 16 PCI clocks
Yes
Yes
00
31:16
Remap of Local to PCI Space into a PCI Address Space. The bits in this register
remap (replace) the local address bits used in decode as the PCI address bits. This
PCI Remap address is used for both Direct Master memory and I/O accesses.
Yes
Yes
0
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