參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 40/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 32
Version 0.93
to be contiguous. The IOP allocates and initializes
inbound message frames in shared IOP memory using
any suitable memory allocation technique. The Host
allocates and initializes outbound message frames in
shared Host memory using any suitable memory
allocation technique. Message frames are a minimum of
64 bytes in length.
I
2
O uses a “push” (write preferred) memory model. That
means that the IOP will write messages and data to the
shared Host memory, and the Host will write messages
and data to shared IOP memory. Software should make
use of burst and DMA transfers whenever possible to
ensure efficient use of the PCI bus for message passing.
Additional
implementation may be found in the
I
2
O Architecture
Specification v1.5
.
information
on
message
passing
3.11.4 Inbound Free List FIFO
The local processor allocates inbound message frames
in its shared memory and can place the address of a
free (available) message frame into the Inbound Free
List FIFO by writing its MFA into the FIFO location
pointed to by the Queue Base Register + Inbound Free
Head Pointer Register. The local processor must then
increment the Inbound Free Head Pointer Register.
A PCI master (Host or another IOP) can obtain the MFA
of a free message frame by reading the Inbound Queue
Port Address (40h of the first PCI Memory Base Address
Register). If the FIFO is empty (no free inbound
message frames are currently available, head and tail
pointers are equal), the MU returns a value of
-1 (FFFFFFFFh). If the FIFO is not empty (head and
tail pointers are not equal), the MU reads the
MFA pointed to by the Queue Base Register + Inbound
Free Tail Pointer Register, returns its value and
increments the Inbound Free Tail Pointer Register. If the
Inbound Free Queue is not empty, and queue
prefetching is enabled (QSR Register bit 3), then the
next entry in the FIFO will be read from the local bus
into a prefetch register. The data for the next PCI read
from this queue will then be provided by the prefetch
register, thus reducing the number of PCI wait states..
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