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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 85/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 77
Version 0.93
4.6.14 (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register
Table 4-74. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register
Field
Description
Read
Write
Value after Reset
3:0
DMA Channel 0 PCI to Local Almost Full (C0PLAF). Number of pairs of full entries
(minus 1) in FIFO before requesting local bus for writes.
(C0PLAF+1) + (C0PLAE+1) should be
≤
FIFO Depth of 32.
Yes
Yes
0
7:4
DMA Channel 0 Local to PCI Almost Empty (C0LPAE). Number of empty entries
(minus 1) in FIFO before requesting local bus for reads.
(C0LPAF+1) + (C0LPAE+1) should be
≤
FIFO depth of 32.
Yes
Yes
0
11:8
DMA Channel 0 Local to PCI Almost Full (C0LPAF). Number of pairs of full entries
(minus 1) in FIFO before requesting PCI bus for writes.
Yes
Yes
0
15:12
DMA Channel 0 PCI to Local Almost Empty (C0PLAE). Number of empty entries
(minus 1) in FIFO before requesting PCI bus for Reads.
Yes
Yes
0
19:16
DMA Channel 1 PCI to Local Almost Full (C1PLAF). Number of full entries (minus 1)
in FIFO before requesting local bus for writes.
(C1PLAF+1) + (C1PLAE+1) should be
≤
FIFO depth of 16.
Yes
Yes
0
23:20
DMA Channel 1 Local to PCI Almost Empty (C1LPAE). Number of empty entries
(minus 1) in FIFO before requesting local bus for reads.
(C1PLAF+1) + (C1PLAE+1) should be
≤
FIFO depth of 16
Yes
Yes
0
27:24
DMA Channel 1 Local to PCI Almost Full (C1LPAF). Number of full entries (minus 1)
in FIFO before requesting PCI bus for writes.
Yes
Yes
0
31:28
DMA Channel 1 PCI to Local Almost Empty (C1PLAE). Number of empty entries
(minus 1) in FIFO before requesting PCI bus for reads.
Yes
Yes
0
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