參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 83/133頁
文件大小： 883K
代理商： PLI9080
SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 75
Version 0.93
4.6.7 (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register
Table 4-68. (DMAPADR1; PCI:98h, LOC:118h) DMA Channel 1 PCI Address Register
Field
Description
Read
Write
Value after Reset
31:0
PCI Data Address Register. Indicates from where in the PCI memory space the DMA
transfers (reads or writes) start.
Yes
Yes
0
4.6.8 (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register
Table 4-69. (DMALADR1; PCI:9Ch, LOC:11Ch) DMA Channel 1 Local Address Register
Field
Description
Read
Write
Value after Reset
31:0
Local Data Address Register. Indicates from where in the local memory space the
DMA transfers (reads or writes) start.
Yes
Yes
0
4.6.9 (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register
Table 4-70. (DMASIZ1; PCI:A0h, LOC:120h) DMA Channel 1 Transfer Size (Bytes) Register
Field
Description
Read
Write
Value after Reset
22:0
DMA Transfer Size (Bytes). Indicates the number of bytes to transfer during a DMA
operation.
Yes
Yes
0
31:23
Reserved.
Yes
No
0
4.6.10 (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register
Table 4-71. (DMADPR1; PCI:A4h, LOC:124h) DMA Channel 1 Descriptor Pointer Register
Field
Description
Read
Write
Value after Reset
0
Descriptor Location. A value of 1 indicates the PCI address space. A value of 0
indicates the local address space.
Yes
Yes
0
1
End of Chain. A value of 1 indicates end of chain. A value of 0 indicates not end of
chain descriptor. (Same as Nonchaining Mode.)
Yes
Yes
0
2
Interrupt after Terminal Count. A value of 1 causes an interrupt to be generated after
the terminal count for this descriptor is reached. A value of 0 disables interrupts from
being generated.
Yes
Yes
0
3
Direction of Transfer. A value of 1 indicates transfers from local bus to PCI bus.
A value of 0 indicates transfers from PCI bus to local bus.
Yes
Yes
0
31:4
Next Descriptor Address. Quad word aligned (Bit [3:0] = 0000).
Yes
Yes
0
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