參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 97/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 5
PCI 9080
PIN DESCRIPTION
PLX Technology, Inc., 1997
Page 89
Version 0.93
Table 5-5. C Bus Mode Interface Pin Description (continued)
C Mode Bus
Symbol
Signal Name
Total
Pins
Pin
Type
Pin
Number
Function
LBE[3:0]#
Byte Enables
4
I/O
TS
12 mA
139-142
Encoded, based on configured bus width, as follows:
32-bit bus
:
For a 32-bit bus, the four byte enables indicate which of the four bytes
are active during a data cycle:
BE3# Byte Enable 3—LD[31:24]
BE2# Byte Enable 2—LD[23:16]
BE1# Byte Enable 1—LD[15:8]
BE0# Byte Enable 0—LD[7:0]
16-bit bus:
For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide BHE#,
A1 and BLE#, respectively:
BE3# Byte High Enable (BHE#)—LD[15:8]
BE2# not used
BE1# Address bit 1 (A1)
BE0# Byte Low Enable (BLE#)—LD[7:0]
8-bit bus:
For an 8-bit bus, BE1# and BE0# are encoded to provide A1and A0,
respectively:
BE3# not used
BE2# not used
BE1# Address bit 1 (A1)
BE0# Address bit 0 (A0)
LCLK
Local Processor Clock
1
I
160
Local clock input
LHOLD
Hold Request
1
O
TP
8 mA
158
Asserted to request use of the local bus. The local bus arbiter asserts
LHOLDA when control is granted.
LHOLDA
Hold Acknowledge
1
I
159
Asserted by the local bus arbiter when control is granted in response to
LHOLD. The bus should not be granted to the PCI 9080 unless
requested by LHOLD.
LRESETo#
Local Bus Reset Out
1
O
TP
8 mA
11
Asserted when the PCI 9080 chip is reset. Used to drive the RESET#
input of the local processor.
READYi#
Ready In
1
I
147
When the PCI 9080 is a bus master, indicates that read data on the bus
is valid or that a write data transfer is complete. Used in conjunction with
the PCI 9080 programmable wait state generator.
READYo#
Ready Out
1
O
DTS
8 mA
148
When a local bus access is made to the PCI 9080, indicates read data
on the bus is valid or a write data transfer is complete. READYo# can be
connected to READYi#.
EOT0#
End of Transfer for
DMA Ch 0
1
I
163
Terminates the current DMA Ch 0 transfer.
EOT1#
End of Transfer for
DMA Ch 1
1
I
164
Terminates the current DMA Ch 1 transfer.
相關PDF資料
PDF描述
PLL0210A PHASE LOCKED LOOP
PLL0210A PHASE LOCKED LOOP
PLL0305A Serial-Input Frequency Synthesizer
PLL1045A Phase-Locked Loop
PLL1070A PHASE LOCKED LOOP
相關代理商/技術參數(shù)
參數(shù)描述
PLI-A10 制造商:Banner Engineering 功能描述:Plastic Fiber Convergent, Core Dia.: 0.5 mm & 9 x 0.25 mm, Fiber Length 2 m, Le
PLIC/DUSB_PHY/AA 制造商:PLDA 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature)
PLIC/DUSB_PHY/XX 制造商:PLD Applications Inc 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature) 制造商:PLDA 功能描述:PROJECT ENCRYPTED LICENSE FOR A SUPERSPEED USB DEVICE CONTR - Virtual or Non-Physical Inventory (Software & Literature)
PLIC/EZDMA/X8/GEN1/XX 制造商:PLD Applications Inc 功能描述:PERMANENT ENCRYPTED LICENSE FOR A X1/X4/X8 PCIE EZDMA IP - Virtual or Non-Physical Inventory (Software & Literature)
PLIC/LITE/X8/GEN1/XX 制造商:PLD Applications Inc 功能描述:PERMANENT ENCRYPTED LICENSE FOR A X1/X4/X8 PCI EXPRESS IP C - Virtual or Non-Physical Inventory (Software & Literature)
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*