參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 39/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 31
Version 0.93
read by an external PCI agent, returns the Inbound Free
List FIFO MFA. An external PCI agent places a
message frame into the Inbound Post List FIFO by
writing its MFA to the inbound queue port location.
3.11.2 Outbound Messages
Outbound messages reside in a pool of message frames
(minimum 64-byte frames) allocated in shared PCI bus
(Host System) memory. The outbound message queue
is comprised of a pair of rotating FIFOs implemented in
local memory. The Outbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in system memory. The Outbound Post List
FIFO holds the MFA of all currently posted messages.
The outbound circular FIFOs are accessed by external
PCI agents through the Outbound Queue Port location
in the PCI address space. The Outbound Queue Port,
when read by an external PCI agent, returns the
Outbound Post List FIFO MFA. An external PCI agent
places free message frames into the Outbound Free List
FIFO by writing the free MFA into the Outbound Queue
Port location.
Memory for the circular FIFOs themselves must be
allocated in local (IOP) memory. The queues base
address is contained in the Queue Base Address
Register (QBAR). Each FIFO entry is a 32 bit data
value. Each read and write of the queue must be a
single 32-bit access.
The circular FIFOs range in size from 4K entries to 64K
entries. All four FIFOs must be the same size and
contiguous. Therefore, the total amount of local memory
needed for circular FIFOs ranges from 64 KB to 1 MB.
FIFO size is specified in the Messaging Queue
Configuration Register (MQCR).
The starting address of each FIFO is based on the
Queue base Address and the FIFO Size, as listed in
Table 3-4.
Table 3-4. Queue Starting Address
FIFO
Starting Address
Inbound Free List
QBAR
Inbound Post List
QBAR + (1 * FIFO Size)
Outbound Post List
QBAR + (2 * FIFO Size)
Outbound Free List
QBAR + (3 * FIFO Size)
3.11.3 I
2
O Pointer Management
The FIFOs always reside in shared local (IOP) memory
and are allocated and initialized by the IOP. Before
enabling I
2
O (MQCR register bit 0 set to 1) the local
processor must initialize the Inbound Post and Free
Head Pointer Registers, the Inbound Post and Free Tail
Pointer Registers, the Outbound Post and Free Head
Pointer Registers, and the Outbound Post and Free Tail
Pointer Registers with the initial offset according to the
FIFO size configured. The Messaging Unit will
automatically add the Queue Base Address to the offset
in each head and tail pointer register. The software can
then enable I
2
O. After initialization, the local software
should not write to the pointers managed by the
MU hardware.
The empty flags are set if the queues are disabled
(MQCR bit 0 = 0) and the head and tail pointers are
equal. This occurs independently of how the head and
tail pointers are set.
An empty flag is cleared, signifying not empty, only if
the queues are enabled and the pointers become not
equal.
If an empty flag is cleared and the queues are enabled,
the empty flag will only be set if the tail pointer is
incremented and the head and tail pointers become
equal.
Full flags are always cleared when the queues are
disabled or the head and tail pointers are not equal.
A full flag is set when the queues are enabled, the head
pointer is incremented, and the head and tail pointers
become equal.
Each circular FIFO has a head pointer and a tail pointer,
which are offsets from the Queue Base Address. Writes
to a FIFO occur at the head of the FIFO and reads
occur from the tail. The head and tail pointers are
incremented by either the local processor or the MU
hardware. The unit that writes to the FIFO also
maintains the pointer. The pointers are incremented
after the FIFO access. Both pointers wrap around to the
first address of the circular FIFO when they reach the
FIFO size, so that the head and tail pointers “chase”
each other around and around in the circular FIFO. The
MU will wrap the pointers automatically for the pointers
that it maintains. IOP software must wrap the pointers
that it maintains. Whenever they are equal, the FIFO is
empty. To prevent overflow conditions, I
2
O specifies
that the number of message frames allocated should be
less than or equal to the number of entries in a FIFO.
(Refer to Figure 3-14 for additional information.)
Each inbound MFA is specified by I
2
O as the offset from
the start of shared local (IOP) memory region 0 to the
start of the message frame. Each outbound MFA is
specified
as
the
offset
location 0x00000000h to the start of the message frame
in shared Host memory. Since the MFA is an actual
address, the message frames themselves do not need
from
Host
memory
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