參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 38/133頁
文件大小： 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 30
Version 0.93
channel interrupt is pending. A Done Status Bit in the
Control/Status Register can be used to determine
whether the interrupt is
A done interrupt
The result of a transfer for a descriptor in a chain
that is not yet complete
The Mode Register of a channel enables a done
interrupt. In chaining mode, a bit in the Next Descriptor
Pointer Register of the channel (loaded from local
memory) specifies whether to generate an interrupt at
the end of the transfer for the current descriptor.
A DMA channel interrupt is cleared by writing a 1 to the
Clear Interrupt bit in the DMA Command/Status
Register.
3.10.3 PCI SERR# (PCI NMI)
The PCI 9080 generates an SERR# pulse if parity
checking is enabled in the PCI Command Register and
it detects an address parity error or the Generate
SERR# Bit in the Interrupt Control/Status Register is 0
and a 1 is written.
The SERR# output can be enabled or disabled with the
PCI Command Register.
3.10.4 Local LSERR# (Local NMI)
The LSERR# interrupt output is asserted if the PCI bus
Target Abort or Master Abort status bit is set in the PCI
Status Configuration Register, a parity error status bit is
set in the PCI Status Configuration Register, or the
messaging outbound free queue overflows.
If parity error checking is enabled in the PCI Command
Register, the PCI 9080 sets the Master Detected Parity
Error Status bit in the PCI Status Register if it detects
one of the following:
A parity error during a PCI 9080 master read
The PCI bus signal PERR# being asserted during
a PCI 9080 master write
The PCI 9080 sets a parity error bit in the PCI Status
Register if it detects a data parity error during a PCI
9080 master read, a data parity error during a slave
write access to the PCI 9080 or an address parity error.
The PCI 9080 Interrupt Control/Status Register can be
used to individually enable or disable LSERR# for an
abort or parity error. LSERR# is a level output that
remains asserted as long as the Abort or Parity Error
Status bits are set.
3.11 I
2
0 COMPATIBLE MESSAGE UNIT
The Messaging Unit supplies two paths for messages,
two inbound FIFOs to receive messages from the
primary PCI bus and two outbound FIFOs to pass
messages to the primary PCI bus. Refer to the
I
2
O
Architecture Specification v1.5
for details.
Figure 3-12 and Figure 3-13 illustrate information about
the I
2
0 architecture.
Outbound Queue
Inbound Queue
Message Frames
Message Frames
IOP Must Have:
CPU
Memory
Messaging Unit
No hardware
changes are
required on
host side
Host CPU
PCI Bus
IOP CPU
IOP
Local
Memory
Physical
System
Memory
IOP = Intelligent I/O processor
Figure 3-12. I
2
O System Architecture
Current Architecture
I O Architecture
OS Specific
Module
Hardware
Device
Module
Hardware
HDM
OSM
Messaging Layer
Hardware
OSM = Operating System Master
HDM = Hardware Device Module
Figure 3-13. I
2
O Software Architecture
3.11.1 Inbound Messages
Inbound messages reside in a pool of message frames
(minimum 64-byte frames) allocated in shared local bus
(IOP) memory. The inbound message queue is
comprised of a pair of rotating FIFOs implemented in
local memory. The Inbound Free List FIFO holds the
message frame addresses (MFA) of available message
frames in local memory. The Inbound Post List FIFO
holds the MFA of all currently-posted messages.
The inbound circular FIFOs are accessed by external
PCI agents through the Inbound Queue Port location in
the PCI address space. The Inbound Queue Port, when
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