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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 76/133頁 |
| 文件大小： | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 68
Version 0.93
4.5.11 (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status
Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status
Field
Description
Read
Write
Value after Reset
0
Enable Local Bus LSERR#. A value of 1 enables the PCI 9080 to assert LSERR#
interrupt output when the PCI bus Target Abort or Master Abort status bit is set in the
PCI Status Configuration Register.
Yes
Yes
0
1
Enable Local Bus LSERR# when a PCI parity error occurs during a PCI 9080 Master
Transfer or a PCI 9080 Slave access.
Yes
Yes
0
2
Generate PCI Bus SERR#. When this bit is set to 0, writing a 1 generates a PCI bus
SERR#.
Yes
Yes
0
3
Mailbox Interrupt Enable. A value of 1 enables a Local Interrupt to be generated when
the PCI bus writes to Mailbox registers 0-3. To clear the Local Interrupt, the Local
master must read the Mailbox. Used in conjunction with Local interrupt enable.
Yes
Yes
0
7:4
Reserved.
Yes
No
0
8
PCI Interrupt Enable. A value of 1 enables PCI interrupts.
Yes
Yes
1
9
PCI Doorbell Interrupt Enable. A value of 1 enables doorbell interrupts. Used in
conjunction with PCI interrupt enable. Clearing the doorbell interrupt bits that caused
the interrupt also clears the interrupt.
Yes
Yes
0
10
PCI Abort Interrupt Enable. A value of 1 enables a master abort or master detect of a
target abort to generate a PCI interrupt. Used in conjunction with PCI interrupt enable.
Clearing the abort status bits also clears the PCI interrupt.
Yes
Yes
0
11
PCI Local Interrupt Enable. A value of 1 enables a local interrupt input to generate a
PCI interrupt. Use in conjunction with PCI interrupt enable. Clearing the local bus
cause of the interrupt also clears the interrupt.
Yes
Yes
0
12
Retry Abort Enable. A value of 1 enables the PCI 9080 to treat 256 Master consecutive
retries to a Target as a Target Abort. A value of 0 enables the PCI 9080 to attempt
Master Retries indefinitely.
Yes
Yes
0
13
A value of 1 indicates the PCI doorbell interrupt is active.
Yes
No
0
14
A value of 1 indicates the PCI abort interrupt is active.
Yes
No
0
15
A value of 1 indicates the local interrupt is active (LINTi#).
Yes
No
0
16
Local Interrupt Output Enable. A value of 1 enables local interrupt output.
Yes
Yes
1
17
Local Doorbell Interrupt Enable. A value of 1 enables doorbell interrupts. Used in
conjunction with Local interrupt enable. Clearing the local doorbell interrupt bits that
caused the interrupt also clears the interrupt.
Yes
Yes
0
18
Local DMA Channel 0 Interrupt Enable. A value of 1 enables DMA Channel 0
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA
status bits also clears the interrupt.
Yes
Yes
0
19
Local DMA Channel 1 Interrupt Enable. A value of 1 enables DMA Channel 1
interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA
status bits also clears the interrupt.
Yes
Yes
0
20
A value of 1 indicates the Local doorbell interrupt is active.
Yes
No
0
21
A value of 1 indicates the DMA Ch 0 interrupt is active.
Yes
No
0
22
A value of 1 indicates the DMA Ch 1 interrupt is active.
Yes
No
0
23
A value of 1 indicates the BIST interrupt is active.
The BIST (built in self test) interrupt is generated by writing a 1 to bit 6 of the
PCI Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the BIST
register for a description of self test.
Yes
No
0
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