參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 72/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 64
Version 0.93
4.4.12 (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to
PCI IO/CFG
Table 4-44. (DMCFGA; PCI:2Ch, LOC:ACh) PCI Configuration Address Register for Direct Master to PCI IO/CFG
Field
Description
Read
Write
Value after Reset
1:0
Configuration Type (00=Type 0, 01=Type 1).
Yes
Yes
0
7:2
Register Number. If different register read/write is needed, this register value must be
programmed and a new PCI configuration cycle must be generated.
Yes
Yes
0
10:8
Function Number.
Yes
Yes
0
15:11
Device Number.
Yes
Yes
0
23:16
Bus Number.
Yes
Yes
0
30:24
Reserved.
Yes
No
0
31
Configuration Enable. A value of 1 allows local to PCI I/O accesses to be converted to
a PCI configuration cycle. The parameters in this table are used to generate the PCI
configuration address.
Yes
Yes
0
4.4.13 (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI to
Local Bus
Table 4-45. (LAS1RR; PCI:F0h, LOC:170h) Local Address Space 1 Range Register for PCI to Local Bus
Field
Description
Read
Write
Value after Reset
0
Memory Space Indicator. A value of 0 indicates local address space 1 maps into PCI
memory space. A value of 1 indicates address space 1 maps into PCI I/O space.
Yes
Yes
0
2:1
If mapped into memory space, encoding is as follows:
2/1 Meaning
0 0
Locate anywhere in 32 bit PCI address space
0 1
Locate below 1 MB in PCI address space
1 0
Locate anywhere in 64 bit PCI address space
1 1
Reserved
If mapped into I/O space, bit 1 must be set to 0.
Bit 2 is included with bits [31:3] to indicate decoding range.
Yes
Yes
0
3
If mapped into memory space, a value of 1 indicates reads are prefetchable (bit has no
effect on the operation of the PCI 9080, but is for system status). If mapped into I/O
space, bit is included with bits [31:2] to indicate decoding range.
Yes
Yes
0
31:4
Specifies which PCI address bits to use for decoding a PCI access to local bus
space 1. Each of the bits corresponds to a PCI address bit. Bit 31 corresponds to
Address bit 31. Write a value of 1 to all bits that must be included in decode and a 0 to
all others (Used in conjunction with PCI Configuration Register Ch 1). Default is 1 MB.
Yes
Yes
FFF0000h
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