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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 69/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 61
Version 0.93
4.4.7 (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region
Descriptor Register
Table 4-39. (LBRD0; PCI:18h, LOC:98h) Local Address Space 0/Expansion ROM Bus Region Descriptor Register
Field
Description
Read
Write
Value after Reset
1:0
Memory Space 0 Local Bus Width. A value of 00 indicates a bus width of 8 bits,
a value of 01 indicates a bus width of 16 bits and a value of 10 or 11 indicates a bus
width of 32 bits.
Yes
Yes
S = 01
J = 11
C = 11
5:2
Memory Space 0 Internal Wait States (data to data; 0-15).
Yes
Yes
0
6
Memory Space 0 Ready Input Enable. A value of 1 enables Ready input. A value of 0
disables the Ready input.
Yes
Yes
0
7
Memory Space 0 BTERM Input Enable. A value of 1 enables BTERM input.
A value of 0 disables the BTERM input. If this bit is set to 0, the PCI 9080 bursts
4 Lword maximum at a time.
Yes
Yes
0
8
Memory Space 0 Prefetch Disable. If mapped into memory space, a value of 0 enables
read prefetching. A value of 1 disables prefetching. If prefetching is disabled, the PCI
9080 disconnects after each memory read.
Yes
Yes
0
9
Expansion ROM Space Prefetch Disable. A value of 0 enables read prefetching.
A value of 1 disables prefetching. If prefetching is disabled, the PCI 9080 disconnects
after each memory read.
Yes
Yes
0
10
Read Prefetch Count Enable. When set to 1 and memory prefetching is enabled, the
PCI 9080 prefetches up to the number of Lwords specified in the prefetch count.
When set to 0, the PCI 9080 ignores the count and continues prefetching until
terminated by the PCI bus.
Yes
Yes
0
14:11
Prefetch Counter. Number of long words to prefetch during memory read cycles (0-15).
A count of zero selects a prefetch of 16 Lwords.
Yes
Yes
0
15
Reserved.
Yes
No
0
17:16
Expansion ROM Space Local Bus Width. A value of 00 indicates a bus width of 8 bits,
a value of 01 indicates a bus width of 16 bits and a value of 10 or 11 indicates a bus
width of 32 bits.
Yes
Yes
S = 01
J = 11
C = 11
21:18
Expansion ROM Space Internal Wait States (data to data; bits 0-15).
Yes
Yes
0
22
Expansion ROM Space Ready Input Enable. A value of 1 enables Ready input. A value
of 0 disables the Ready input.
Yes
Yes
0
23
Expansion ROM Space BTERM Input Enable. A value of 1 enables BTERM input.
A value of 0 disables the BTERM input. If this bit is set to 1, the PCI 9080 bursts 4
Lword maximum at a time.
Yes
Yes
0
24
Memory Space 0 Burst Enable. A value of 1 enables bursting. A value of 0 disables
bursting. If burst is disabled, the local bus performs continuous single cycles for burst
PCI read/write cycles.
Yes
Yes
0
25
Extra Long Load from EEPROM. A value of 1 loads the Subsystem ID and Local
Address Space 1 registers. A value of 0 indicates not to load them.
Yes
No
0
26
Expansion ROM Space Burst Enable. A value of 1 enables bursting. A value of 0
disables bursting. If burst is disabled, the local bus performs continuous single cycles
for burst PCI read/write cycles.
Yes
Yes
0
27
Direct Slave PCI Write Mode. A value of 0 indicates the PCI 9080 should disconnect
when the Direct Slave write FIFO is full. A value of 1 indicates the PCI 9080 should de-
assert TRDY# when the write FIFO is full.
Yes
Yes
0
31:28
PCI Target Retry Delay Clocks. Contains the value (multiplied by 8) of the number of
PCI bus clocks after receiving a PCI local read or write access and not successfully
completing a transfer. Only pertains to Direct Slave writes when bit 27 is set to 1.
Yes
Yes
4
(32 clocks)
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