參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 43/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 35
Version 0.93
interrupt. The interrupt is recorded in the Queue Status
Control (QSR) Register.
From the time that the PCI write transaction is received
until the data is written into local memory and the
Outbound Free Head Pointer Register is incremented,
any PCI direct slave access to the PCI 9080 is issued a
RETRY.
Table 3-5. Circular FIFO Summary
FIFO
Name
PCI
Port
Generate PCI
Interrupt
Generate Local
Interrupt
Head Pointer
Maintained by
Tail Pointer
Maintained by
Inbound Free
List FIFO
Inbound Queue
Port (Host read)
No
No
Local
processor
MU hardware
Inbound Post
List FIFO
Inbound Queue
Port (Host write)
No
Yes, when Port
is written
MU hardware
Local
processor
Outbound Post
List FIFO
Outbound Queue
Port (Host read)
Yes, when FIFO
is not empty
No
Local
processor
MU hardware
Outbound Free
List FIFO
Outbound Queue
Port (Host write)
No
Yes, (LSERR) when
FIFO full
MU hardware
Local
processor
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