參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 64/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 56
Version 0.93
4.3.20 (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register
Table 4-30. (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register
Field
Description
Read
Write
Value after Reset
7:0
Interrupt Pin Register. Indicates which interrupt pin the device uses. The following
values are decoded:
0 = No Interrupt Pin
1 = INTA#
2 = INTB#
3 = INTC#
4 = INTD#
Yes
Local/
EEPROM
1
4.3.21 (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register
Table 4-31. (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register
Field
Description
Read
Write
Value after Reset
7:0
Min_Gnt. Specifies how long a burst period the device needs, assuming a clock rate
of 33 MHz. Value is multiple of 1/4 μsec increments.
Yes
Local/
EEPROM
0
4.3.22 (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register
Table 4-32. (PCIMLR; PCI:3Fh, LOC:3Fh) PCI Max_Lat Register
Field
Description
Read
Write
Value after Reset
7:0
Max_Lat. Specifies how often the device must gain access to the PCI bus. Value is
multiple of 1/4 μsec increments.
Yes
Local/
EEPROM
0
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