參數(shù)資料
型號(hào)： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 37/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 29
Version 0.93
local access to clear the master abort and target abort
interrupt bits in the PCI Configuration Status Register.
Bits [26:24] of the Interrupt Control/Status Register are
latched at the time of a target abort interrupt or a master
abort interrupt. They provide information as to who was
master when an abort occurred. The PCI 9080 updates
these bits whenever an abort occurs.
3.10.2 Local Interrupts (LINTo#)
A PCI 9080 Local Interrupt (LINTo#) can be generated
by one of the following:
The PCI to Local Doorbell/Mailboxes Register
access
A PCI BIST interrupt, the DMA done interrupt
The DMA terminal count is reached
The DMA abort interrupt or messaging outbound
post queue not empty
LINTo#, or individual sources of an interrupt, can be
enabled or disabled with the PCI 9080 Interrupt
Control/Status Register. The Interrupt Control/Status
Register also provides interrupt status for each source of
the interrupt.
The PCI 9080 local interrupt is a level output. An
interrupt can be cleared by disabling the interrupt
enable bit of a source or by clearing the cause of an
interrupt.
3.10.2.1 Local to PCI Doorbell Interrupt
A local bus master can generate a PCI bus interrupt by
writing to the Local to PCI Doorbell Register. The PCI
host processor can then read the PCI 9080 Interrupt
Control/Status Register to determine that a doorbell
interrupt is pending. It can then read the PCI 9080 Local
to PCI Doorbell Register.
Each bit in the Local to PCI Doorbell register is
individually controlled. Bits in the Doorbell Register can
only be set by the local side. From the local side, writing
a 1 to any bit position sets that bit and writing a 0 to a bit
position has no effect. Bits in the Local to PCI Doorbell
Register can only be cleared from the PCI side. From
the PCI side, writing a 1 to any bit position clears that bit
and writing a 0 to a bit position has no effect.
The interrupt remains asserted as long as any of the
Local to PCI Doorbell Register bits are set and the PCI
Doorbell interrupt is enabled.
To prevent race conditions when the PCI bus is
accessing the Doorbell Register (or any configuration
register), the PCI 9080 automatically de-asserts
READYo# to prevent local bus accesses.
3.10.2.2 PCI to Local Doorbell Interrupt
A PCI bus master can generate a local bus interrupt by
writing to the PCI to Local Doorbell Register. The Local
processor can then read the PCI 9080 Interrupt
Control/Status Register to determine that a doorbell
interrupt is pending. It can then read the PCI 9080 PCI
to Local Doorbell Register.
Each bit in the PCI to Local Doorbell register is
individually controlled. Bits in the Doorbell Register can
only be set by the PCI side. From the PCI side, writing
a 1 to any bit position sets that bit and writing a 0 to a bit
position has no effect. Bits in the PCI to Local Doorbell
Register can only be cleared from the local side. From
the local side, writing a 1 to any bit position clears
that bit and writing a 0 to a bit position has no effect.
Note: If the local side cannot clear the Doorbell Interrupt,
do not use the PCI to Local Doorbell Register.
The interrupt remains asserted as long any of the PCI to
Local Doorbell Register bits are set and the Local
Doorbell interrupt is enabled.
To prevent race conditions when the local bus is
accessing the Doorbell Register (or any configuration
register), the PCI 9080 automatically issues a RETRY to
the PCI bus.
3.10.2.3 Built In Self Test Interrupt (BIST)
A PCI bus master can generate a local bus interrupt by
performing a PCI Type 0 configuration write to a bit in
the PCI BIST register. The local processor can then
read the PCI 9080 Interrupt Control/Status Register to
determine that a BIST interrupt is pending.
The interrupt remains asserted as long as the bit is set
and the BIST interrupt is enabled. The local bus then
resets the bit when BIST is complete. PCI Host software
may fail the device if the bit is not reset after 2 seconds.
Note: The PCI 9080 does not have internal BIST.
3.10.2.4 DMA Channel 0/1 Interrupts
A DMA channel can generate a PCI or local bus
interrupt when done (transfer complete) or after a
transfer is complete for a descriptor in chaining mode.
A bit in the DMA mode register determines whether to
generate a PCI or local interrupt. The local or PCI
processor can then read the PCI 9080 Interrupt
Control/Status Register to determine whether a DMA
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