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參數(shù)資料
| 型號(hào)： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 82/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 74
Version 0.93
4.6.6 (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register
Table 4-67. (DMAMODE1; PCI:94h, LOC:114h) DMA Channel 1 Mode Register
Field
Description
Read
Write
Value after Reset
1:0
Local Bus Width. A value of 00 indicates a bus width of 8 bits, a value of 01 indicates a
bus width of 16 bits and a value of 10 or 11 indicates a bus width of 32 bits.
Yes
Yes
S = 01
J = 11
C = 11
5:2
Internal Wait States (data to data).
Yes
Yes
0
6
Ready Input Enable. A value of 1 enables Ready input. A value of 0 disables the Ready
input.
Yes
Yes
0
7
BTERM Input Enable. A value of 1 enables BTERM input. A value of 0 disables the
BTERM input. If this bit is set to 0, the PCI 9080 bursts 4 Lword maximum at a time.
Yes
Yes
0
8
Local Burst Enable. A value of 1 enables bursting. A value of 0 disables local bursting.
If burst is disabled, the local bus performs continuous single cycles for burst PCI
read/write cycles.
Yes
Yes
0
9
Chaining. A value of 1 indicates chaining mode enabled. For chaining mode, the DMA
source address, destination address and byte count are loaded from memory in PCI or
Local address spaces. A value of 0 indicates nonchaining mode enabled.
Yes
Yes
0
10
Done Interrupt Enable. A value of 1 enables interrupt when done. A value of 0 disables
interrupt when done. If the DMA Clear Count Mode is enabled, the interrupt won’t
occur until the byte count is cleared.
Yes
Yes
0
11
Local Addressing Mode. A value of 1 indicates local address LA[31:2] to be held
constant. A value of 0 indicates local address is incremented.
Yes
Yes
0
12
Demand Mode. A value of 1 causes the DMA controller to operate in demand mode. In
demand mode the DMA controller transfers data when its DREQ# input is asserted. It
asserts DACK# to indicate the current local bus transfer is in response to the DREQ#
input. The DMA controller transfers Lwords (32bits) of data. This may result in multiple
transfers for an 8- or 16-bit bus.
Yes
Yes
0
13
Write and Invalidate Mode for DMA Transfers. When set to 1, the PCI 9080 performs
Write and Invalidate cycles to the PCI bus. The PCI 9080 supports Write and
Invalidate sizes of 8 or 16 Lwords. The size is specified in the PCI Cache Line Size
Register. If a size other than 8 or 16 is specified, the PCI 9080 performs write transfers
rather than Write and Invalidate transfers. Transfers must start and end at the Cache
Line Boundaries.
Yes
Yes
0
14
DMA EOT (End of Transfer) Enable. A value of 1 enables EOT output pin. A value of 0
disables the EOT output pin.
Yes
Yes
0
15
DMA Stop Data Transfer Mode. A value of 0 BLAST terminates DMA transfer. A value
of 1 indicates EOT asserted or DREQ# negated during demand mode DMA terminates
the DMA transfer.
Yes
Yes
0
16
DMA Clear Count Mode. When set to 1, the byte count in each chaining descriptor, if it
is in local memory, is cleared when the corresponding DMA transfer is complete.
Note: If chaining descriptor is in PCI memory, the count will not be cleared.
Yes
Yes
0
17
DMA Channel 1 Interrupt Select. A value of 1 routes the DMA Channel 1 interrupt to
the PCI interrupt. A value of 0 routes the DMA Channel 1 interrupt to the local bus
interrupt.
Yes
Yes
0
31:18
Reserved.
Yes
No
0
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