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參數(shù)資料
| 型號： | PLI9080 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | PCI I/O ACCELERATOR |
| 中文描述： | 的PCI I / O加速器 |
| 文件頁數(shù)： | 18/133頁 |
| 文件大?。?/td> | 883K |
| 代理商： | PLI9080 |
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SECTION 3
PCI 9080
FUNCTIONAL DESCRIPTION
PLX Technology, Inc., 1997
Page 10
Version 0.93
3. FUNCTIONAL DESCRIPTION
3.1 RESET
3.1.1 PCI Bus Input RST#
The PCI bus RST# input causes all PCI bus outputs to
float, resets the entire PCI 9080 and causes the local
reset output, LRESETo#, to be asserted.
3.1.2 Local Bus Input LRESETi#
When asserted, the LRESETi# input resets the local bus
portion of the PCI 9080, clears all local configuration
registers and causes the LRESETo# output to be
asserted.
3.1.3 Local Bus Output LRESETo#
LRESETo# is asserted when PCI bus RST# input is
asserted, the LRESETi# input is asserted, or the
software reset bit in the Init Control Register is set to 1.
3.1.4 Software Reset
A host on the PCI bus can set the software reset bit in
the Init Control Register to reset the PCI 9080 and
assert the LRESETo# output. The PCI configuration
registers will not be reset. When the software reset bit is
set, the PCI 9080 responds to PCI accesses, but not to
local bus accesses. The PCI 9080 remains in this reset
condition until the PCI host clears the bit.
Note: The local side cannot clear this reset bit because
the local bus is in a reset state.
3.2 PCI 9080 INITIALIZATION
The
programmed by an optional serial EEPROM and/or by a
local processor.
PCI
9080
configuration
registers
can
be
Note: The internal configuration register can also be
accessed by the PCI host processor after power up
initialization.
3.2.1 EEPROM Initialization
During serial EEPROM initialization, the PCI 9080
response to PCI target accesses is RETRY. During
serial EEPROM initialization, the PCI 9080 response to
a local processor is to hold off READYo#.
3.2.2 Local Initialization
The PCI 9080 issues a RETRY to all PCI accesses until
the "Local Init Done bit" in the Init Control Register is
set. The "Init Done bit" is programmable through local
bus configuration accesses. If this bit is not going to be
set by a local processor, then NB# input should be tied
low. Holding NB# input low externally forces the Local
Init Done bit to 1.
The PCI 9080 default values are used if a serial
EEPROM is not present and the local "Init Status" bit is
set to a “1” by holding the NB# input low or set by the
local processor.
3.3 EEPROM
After reset, the PCI 9080 attempts to read the serial
EEPROM to determine its presence. An active low
start bit indicates the serial EEPROM is present (PCI
9080 supports 93CS46 (1K) or 93CS56 (2K), selectable
by way of the EESEL pin). (Refer to the manufacturer’s
data sheet for the particular serial EEPROM being
used.) The first word is then checked to verify the serial
EEPROM is programmed. If the first word (16 bit) is all
1s, a blank serial EEPROM PCI 9080 will use default
values instead.
The serial EEPROM can be read or programmed from
the PCI or local bus. Bits [27:24] of the serial EEPROM
Control Register controls the PCI 9080 pins that enable
the reading or writing of serial EEPROM data bits.
(Refer to the manufacturer’s data sheet for the particular
serial EEPROM being used.)
The PCI 9080 has three serial EEPROM load options:
Short Load Mode—The SHORT# input pin is pulled
down and the PCI 9080 loads 5 Lwords from the
serial EEPROM
Long Load Mode—The SHORT# input pin is pulled
up, bit 25 of the “Local Bus Region Descriptor
Register [LOC 98h]” is set to 0 and the PCI 9080
loads 17 Lwords from the serial EEPROM
Extra Long Load Mode—The SHORT# input pin is
pulled up, bit 25 of the “Local Bus Region Descriptor
Register [LOC 98h]” is set to 1 during Long Load
from the serial EEPROM and the PCI 9080 loads
21 Lwords from the serial EEPROM
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