參數(shù)資料
型號： PLI9080
廠商： Electronic Theatre Controls, Inc.
英文描述： PCI I/O ACCELERATOR
中文描述： 的PCI I / O加速器
文件頁數(shù)： 67/133頁
文件大?。?/td> 883K
代理商： PLI9080
SECTION 4
PCI 9080
REGISTERS
PLX Technology, Inc., 1997
Page 59
Version 0.93
4.4.4 (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register
Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register
Field
Description
Read
Write
Value after Reset
0
Configuration Register Big Endian Mode. A value of 1 specifies use of Big Endian data
ordering for local accesses to the configuration registers. A value of 0 specifies Little
Endian ordering. Big Endian mode can be specified for configuration register accesses
by asserting the BIGEND# pin during the address phase of the access.
Yes
Yes
0
1
Direct Master Big Endian Mode. A value of 1 specifies use of Big Endian data ordering
for Direct Master accesses. A value of 0 specifies Little Endian ordering. Big Endian
mode can be specified for Direct Master accesses by asserting the BIGEND# input pin
during the address phase of the access.
Yes
Yes
0
2
Direct Slave Address Space 0 Big Endian Mode. A value of 1 specifies use of Big
Endian data ordering for Direct Slave accesses to Local Address space 0. A value of 0
specifies Little Endian ordering.
Yes
Yes
0
3
Direct Slave Address Expansion ROM 0 Big Endian Mode. A value of 1 specifies use
of Big Endian data ordering for Direct Slave accesses to Expansion ROM. A value of 0
specifies Little Endian ordering.
Yes
Yes
0
4
Big Endian Byte Lane Mode. A value of 1 specifies that in Big Endian mode, use byte
lanes 31:16 for a 16 bit local bus and byte lanes 31:24 for an 8 bit local bus. A value
of 0 specifies that in Big Endian mode, byte lanes 15:0 be used for a 16 bit local bus
and byte lanes 7:0 for an 8 bit local bus.
Yes
Yes
0
5
Direct Slave Address Space 1 Big Endian Mode. A value of 1 specifies use of Big
Endian data ordering for Direct Slave accesses to local Address Space 1. A value of 0
specifies Little Endian ordering.
Yes
Yes
0
6
DMA Channel 1 Big Endian Mode. A value of 1 specifies use of Big Endian data
ordering for DMA Channel 1 accesses to the local Address Space. A value of 0
specifies Little Endian ordering.
Yes
Yes
0
7
DMA Channel 0 Big Endian Mode. A value of 1 specifies use of Big Endian data
ordering for DMA Channel 0 accesses to the Local Address space. A value of 0
specifies Little Endian ordering.
Yes
Yes
0
31:8
Reserved.
Yes
No
0
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