Interrupt Controller
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
7-3
ICRs.
For an interrupt to be successfully processed, stack RAM must be available. A programmable chip select
is often used for the RAM, in which case, the RAM is not immediately available at startup. Thus, no
interrupts are recognized until PIVR is initialized. The RAM chip select and system stack should be set up
before this initialization.
If more than one interrupt source has the same interrupt priority level (IPL), the interrupt controller daisy
chains the interrupts with the priority order following the bit placement in the PIWR, with INT1 having
the highest priority and SWTO having the lowest priority, as shown in
Figure 7-8.
7.2.1
Interrupt Controller Registers
This section describes the registers associated with the interrupt controller.
Table 7-2 gives the
nomenclature used for the interrupt and power management registers.
Table 7-2. Interrupt and Power Management Register Mnemonics
Mnemonic or Portion Thereof
Description
INT1, INT2, INT3, INT4, INT5, INT6
External interrupt signals 1–6.
TMR0, TMR1, TMR2, TMR3
Timers 3–0 from timer module
USB0, USB1, USB2, USB3, USB4, USB5,
USB6, USB7
USB endpoint 0–7
UART1, UART2
UART1, UART2 modules
PLIP
PLIC 2-KHz periodic interrupt, 2B+D data
PLIA
PLIC asynchronous and maintenance channels interrupt
DMA
DMA controller interrupt
ETx
Ethernet module transmit data interrupt
ERx
Ethernet module receive data interrupt
ENTC
Ethernet module non-time-critical interrupt
QSPI
Queued serial peripheral interface
IPL2, IPL1, IPL0
Interrupt priority level bits 2–0
PI
Pending interrupt
PDN
Power down enable
WK
Wakeup enable
SWTO
Software watchdog timer time out