Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-27
13.5.15 GCI Monitor Channel Transmit Status Register (PGMTS)
All bits in this register are read only and are cleared on hardware or software reset.
The PGMTS register contains the monitor channel status bits for each of the four transmit ports on the
MCF5272.
76543
210
Field
ACK3
ACK2
ACK1
ACK0
AB3
AB2
AB1
AB0
Reset
0000_0000
R/W
Read Only
Addr
MBAR + 0x371
Figure 13-27. GCI Monitor Channel Transmit Status Register (PGMTS)
Table 13-10. PGMTS Field Descriptions
Bits
Name
Description
7
ACK3
Acknowledge, port 3.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has transmitted the previous monitor channel information.
Automatically cleared by the CPU reading the register. The clearing of this bit by reading this register also
clears the aperiodic GMT interrupt.
6
ACK2
Acknowledge, port 2. See ACK3.
5
ACK1
Acknowledge, port 1. See ACK3.
4
ACK0
Acknowledge, port 0. See ACK3.
3
AB3
Abort, port 3.
0 Default reset value.
1 Indicates to the CPU that the GCI controller has aborted the current message. This bit is automatically
cleared by the CPU reading the register. When the GCI controller sets this bit, it also clears the AR bit in the
PGMTA register, the ACK bit in the GMTS register, and the L and R bits in the PnGMT register.
2
AB2
Abort, port 2. See AB3.
1
AB1
Abort, port 1. See AB3.
0
AB0
Abort, port 0. See AB3.