Queued Serial Peripheral Interface (QSPI) Module
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
14-12
Freescale Semiconductor
14.5.3
QSPI Wrap Register (QWR)
15
14
13
12
11
8
7
4
3
0
Field
HALT WREN
WRTO CSIV
ENDQP
–
NEWQP
Reset
0000_0000_0000_0000
R/W
Address
MBAR + 0x00A8
Figure 14-7. QSPI Wrap Register (QWR)
Table 14-5. QWR Field Descriptions
Bits
Name
Description
15
HALT
Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has
completed execution of the current command.
14
WREN
Wraparound enable. Enables wraparound mode.
0 Execution stops after executing the command pointed to by QWR[ENDQP].
1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed
to by QWR[NEWQP] and continue execution.
13
WRTO
Wraparound location. Determines where the QSPI wraps to in wraparound mode.
0 Wrap to RAM entry zero.
1 Wrap to RAM entry pointed to by QWR[NEWQP].
12
CSIV
QSPI_CS inactive level.
0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM
entry during a transfer (that is, inactive state is 0, chip selects are active high).
1 QSPI chip select outputs return to one when not driven from the value in the current command RAM
entry during a transfer (that is, inactive state is 1, chip selects are active low).
11–8
ENDQP
End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.
7–4
CPTQP
Completed queue entry pointer. Points to the RAM entry that contains the last command to have been
completed. This field is read only.
3–0
NEWQP
Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a
transfer.