System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
6-9
Table 6-6 details the interaction between the PDN and WK bits for the USB and USART modules.
10
USBWK
USB wakeup enable. Allows clocking to the USB module to be restored when a change in signal level
is detected on USD_D+ or INT1/USB_WOR. See
Table 6-6 for a description of the interaction between
the PDN and WK bits.
0 Wakeup disabled.
1 Wakeup enabled. USBPDN must also be set.
9
UART1WK
UART1 wakeup enable. Allows clocking to the UART1 module to be restored when a change in signal
level is detected on UART1RxD. See
Table 6-6 for a description of the interaction between the PDN and
WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART1PDN must also be set.
8
UART0WK
UART0 wakeup enable. Allows clocking to the UART0 module to be restored when a change in signal
level is detected on UART0RxD. See
Table 6-6 for a description of the interaction between the PDN and
WK bits.
0 Wakeup disabled.
1 Wakeup enabled. UART0PDN must also be set.
7-6
—
Reserved, should be cleared.
5
MOS
Main oscillator stop. Allows the MCF5272 to be put into stop mode, in which internal clocking is stopped
to the entire processor. To enter stop mode, the user must write to the ALPR and then execute a STOP
on-chip modules in power down mode. After setting this bit, a write access must be made to the ALPR
register to actually enter stop mode. D[31:0] are driven low, and other bus signals are negated. Stop
mode is exited when an interrupt is detected on one the external interrupt pins, INT[6:1].
0 Stop mode disabled.
1 Stop mode enabled.
4
SLPEN
Sleep enable. Allows the MCF5272 to be put into sleep mode in which internal clocking to the CPU is
disabled.To enter sleep mode, the user must write to the ALPR and then execute a STOP instruction.
disabled through the appropriate PDN bits. After SLPEN is set, a write access must be made to ALPR
to actually enter sleep mode. D[31:0] are driven low, and other bus signals are negated. Sleep mode is
exited when an interrupt is detected from an on-chip peripheral or one of the external interrupt pins,
INT[6:1].
0 Sleep mode disabled.
1 Sleep mode enabled.
3-0
—
Reserved, should be cleared.
Table 6-6. USB and USART Power Down Modes
PDN
WK
Description
0
X
Module powered up and operating normally.
1
0
Module in power down and can only be reactivated by clearing PDN.
1
Module in power down and can be reactivated by clearing PDN or detecting signal on the receive pins.
Table 6-5. PMR Field Descriptions (continued)
Bits
Field
Description