Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-3
frame sync (offset with respect to the port 1 GCI/IDL block). Port 3 can also have dedicated data
common frame sync and clock, but two sets of serial data-in and data-out pins.
The MCF5272 PLIC provides two sets of D-channel arbitration control pins:
DREQ0 and DGNT0 for pin set 0
DREQ1 and DGNT1 for pin set 1
Because pin set 1 connects ports 1, 2, and 3, these ports do not have D-channel arbitration control signals.
13.2
GCI/IDL Block
This section describes the GCI/IDL block.
13.2.1
GCI/IDL B- and D-Channel Receive Data Registers
Figure 13-2. GCI/IDL Receive Data Flow
The maximum data rate received for each GCI/IDL port is 144 Kbps: the sum of two 64-Kbps B channels
and one 16-Kbps D-channel. Frames of B1 and B2 channels are packed together to form longwords (32
bits). Frames of D-channels are packed together to form bytes. For channels B and D, this requires CPU
service at a 2-KHz rate, because it requires four frames to fill the 32-bit B-channel register and the 8-bit
D-channel register.
The CPU should service the B1 and B2 registers once every 500
μS. Overrun conditions can be avoided
only if the CPU services these registers in a timely manner.
The MCF5272 has 4 GCI/IDL interfaces. Thus the theoretical maximum is twelve 32-bit data registers to
be read. For most applications the typical number is less.
D Channel
B1 Shift Register
B2 Shift Register
D Shift Register
DIN
DCL
B2 Channel
B1 Channel
32
8
Internal Bus
Demultiplexing
Circuitry