Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-40
Freescale Semiconductor
13.6.4
Example 2: ISDN SOHO PBX with Ports 1, 2, and 3
In this example, port 0 is not used. The port 0 pins are multiplexed with UART0 and in this example, port 0
is used to connect to an external transceiver to provide an RS232 interface. Port 1 is programmed in slave
mode and an external U (or S/T) transceiver is connected to port 1. Port 2 and port 3 are used to connect
up to four external PCM CODECs.
Figure 13-39. ISDN SOHO PABX Example
In the above example, Freescale’s MC14LC5480 CODECs and MC145572 U transceiver are shown. The
U transceiver in this example is connected to port 1 and the FSC1 frame sync signal is used exclusively
for synchronizing the data on the U transceiver’s IDL interface. CODECs 1 and 2 are connected to delayed
frame sync 2, DFSC2, which is the output of programmable delay 2. Programmable delay 2 generates a
delayed frame sync with reference to FSC1. Similarly CODECs 3 and 4 are connected to DFSC3 which is
the output of programmable delay 3. Programmable delay 3 generates a delayed frame sync also with
reference to FSC1. The MC14LC5480 CODECs, when in IDL mode, may be programmed using the FSR
pin to select whether the CODEC is receiving and transmitting on the B1 or the B2 time slot (see
MC14LC5480 data sheet for further information).
Figure 13-40 shows the IDL bus timing relationship of the CODECs and U transceiver when in standard
IDL2 10-bit mode with a common frame sync.
UART0
Din1
Dout1
FSC1
DCL1
MC145572
MC14LC5480
CODEC 2
CODEC 3
Interface1
DFSC2
DFSC3
CODEC 4
Tx
DT
Rx
DR
CODEC 1
MC14LC5480
BCLKT
FST
IDL SYNC
IDL CLK
MCF5272
FSR
GND
BCLKR
Vdd
FSR
GND
BCLKR
Vdd
FSR
Vdd
BCLKR
RS232
Transceiver
FSR
Vdd
BCLKR