Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
19-16
Freescale Semiconductor
K9
CS0/Boot
—
CS0/Boot
Chip select 0
O
K10
CS1
—
CS1
Chip select 1
O
K11
D3
PC3
—
D3/PC3
D3/port C bit 3
I/O
K12
D4
PC4
—
D4/PC4
D4/port C bit 4
I/O
K13
D5
PC5
—
D5/PC5
D5/port C bit 5
I/O
K14
D6
PC6
—
D6/PC6
D6/port C bit 6
I/O
L1
PA11
—
QSPI_CS1
—
PA11/QSPI_CS1
Port A bit 11/QSPI chip
select 1
I/O
L2
PA12
DFSC2
—
PA12/DFSC2
Port A bit 12/Delayed
frame sync 2
I/O
L3
PA13
DFSC3
—
PA13/DFSC3
Port A bit 13/Delayed
frame sync 3
I/O
L4
FSC1/FSR1/
DFSC1
—
FSC1/FSR1/DFSC1
PLIC port 1 IDL FSR/GCI
FSC1/Generated frame
sync 1 Out
I/O
L5
QSPI_CLK/
BUSW1
—
QSPI_CLK / BUSW1
QSPI serial clock/CS0
bus width bit 1
O
L6
TIN0
—
TIN0
Timer 0 input
I
L7
E_Tx CLK
—
E_Tx CLK
Ethernet Tx clock
I
L8
PB10
E_TxD1
—
PB10/E_TxD1
Port B bit 10/Tx data bit 1
(100 Base-T Ethernet
only)
I/O
L9
PB14
E_RxER
—
PB14/E_RxER
Port B bit 14/Receive
Error (100 Base-T
Ethernet only)
I/O
L10
E_CRS
—
E_CRS
Carrier sense (100
base-T Ethernet only)
I
L11
CS5
—
CS5
Chip select 5
O
L12
D0
PC0
—
D0/PC0
D0/port C bit 0
I/O
L13
D1
PC1
—
D1/PC1
D1/port C bit 1
I/O
L14
D2
PC2
—
D2/PC2
D2/port C bit 2
I/O
M1
DCL1/
GDCL1_OUT
—
DCL1/GDCL1_OUT
PLIC ports 1, 2, 3 data
clock/Generated DCL out
I/O
M2
PA14
DREQ1
—
PA14/DREQ1
Port A bit 14/PLIC port 1
IDL D-channel request
I/O
M3
PA15_INT6
DGNT1_INT6
—
PA15_INT6/DGNT1_INT6
Port A bit 15/PLIC port 1
D-channel grant/Interrupt
6 input
I/O
Table 19-2. Signal Name and Description by Pin Number (Sheet 6 of 8)
Map
BGA
Pin
Pin Functions
Name
Description
I/O
0 (Reset)
1
2
3