Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-9
PST3
—
Internal processor status
3
D3
O
4
30
PWM_OUT0
—
PWM output compare 0
N5
O
4
30
QSPI_CLK/
BUSW1
—
QSPI serial clock/CS0
bus width bit 1
L5
O
4
30
QSPI_CS0/
BUSW0
—
QSPI peripheral chip
select 0/CS0 bus width
bit 0
M5
O
2
30
QSPI_Din
—
QSPI data input
P4
I
QSPI_Dout/
WSEL
—
QSPI data output/Bus
width selection
N4
I/O
4
30
R/W
—
Read/Write
P14
O
10
30
RAS0
—
SDRAM row select
strobe
A10
O
10
30
RSTI
—
Device reset
M12
I
RSTO
—
Reset output strobe
F4
O
4
30
SDBA0
—
SDRAM bank 0 select
J14
O
10
30
SDBA1
—
SDRAM bank 1 select
H12
O
10
30
SDCLK
—
SDRAM (bus) clock,
Same frequency as CPU
clock
E14
O
10
30
SDCLKE
—
SDRAM clock enable
D13
O
10
30
SDCS/
CS7
—
SDRAM chip select/CS7
B10
O
10
30
SDWE
—
SDRAM write enable
B9
O
10
30
BYPASS
—
Bypass internal test
mode
M13
O
4
30
MTMOD4
TCK
PSTCLK
—
JTAG test clock in/
BDM PSTCLK output
C4
I/O
4
30
TDI
DSI
—
JTAG test data in/BDM
data in
A4
I
TDO
DSO
—
JTAG test data out
/BDM data out
D5
O
4
30
TEA
—
BDM debug transfer error
acknowledge
A3
I
TEST
—
Device test mode enable
E6
I
TIN0
—
Timer 0 input
L6
I
TMS
BKPT
—
JTAG test mode/BDM
select breakpoint input
B4
I
Table 19-1. Signal Descriptions Sorted by Function (Sheet 7 of 8)
Configured
by
(see notes)1
Pin Functions
Description
Map
BGA
Pin
I/O
Drive
(mA)
Cpf
0 (Reset)
1
2
3