Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
12-24
Freescale Semiconductor
4
IN_EOT
End of transfer. This bit is set when the end of a transfer has been reached for an IN endpoint.
An EOT interrupt is generated when a packet with a size less than the maximum packet size or
the first zero-length packet following maximum size packets is sent.
0 No interrupt pending
1 Transfer completed
3
IN_EOP
End of packet. This bit is set when a packet has been sent successfully for endpoint 0 IN.
0 No interrupt pending
1 IN packet sent successfully
2
UNHALT
Unhalt. This bit is set when the endpoint 0 HALT_ST bit is cleared by a SETUP packet or USB
reset.
0 No interrupt pending
1 Endpoint halt cleared
1
HALT
Halt. This bit is set when the endpoint 0 HALT_ST bit is set due to a STALL response to the host.
0 No interrupt pending
1 Endpoint halted
0
IN_LVL
IN FIFO threshold level. This bit indicates that the FIFO level has fallen below the level set in the
EPCTL0 register.
0 No interrupt pending
1 IN FIFO threshold level reached
Table 12-14. EP0IMR and EP0ISR Field Descriptions (continued)
Bits
Name
Description