Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
12-20
Freescale Semiconductor
12.3.2.14 USB Endpoint 1–7 Control Register (EPnCTL)
Figure 12-17. USB Endpoint 1-7 Control Register (EP
nCTL)
Table 12-13 lists the field descriptions for the USB endpoint 1–7 control register.
15
8
Field
—
Reset
0000_0000
R/W
76543
210
Field CRC_ERR ISO_MODE
—
FIFO_LVL
IN_DONE
STALL
Reset
0000_0004
R/W
Addr
MBAR + 0x1052, 0x1056, 0x105A, 0x105E, 0x1062, 0x1066, 0x106A
Table 12-13. EP
nCTL Field Descriptions
Bits
Name
Description
15–8
—
Reserved, should be cleared.
7
CRC_ERR
CRC error generation enable. Enables CRC error generation for debug and test purposes. To use this
feature, the DEBUG bit must be set. Enabling this bit causes a CRC error on the next non-zero-length
data packet transmitted. The CRC_ERR bit must be set again in order to generate another CRC error.
This bit is only valid for IN endpoints. This command bit is write only and always returns 0 when read.
0 Default Value
1 CRC error generation if DEBUG = 1
6
ISO_MODE Isochronous transfer mode. This bit must be set when the endpoint is configured for isochronous
mode.
0 Non-isochronous transfer mode
1 Isochronous transfer mode
5–4
—
Reserved, should be cleared.
3–2
FIFO_LVL
Endpoint n FIFO level for interrupt. This field selects the FIFO level to generate a FIFO_LVL interrupt.
The FIFO_LVL interrupt is generated when the FIFO fills above (OUT) or falls below (IN) the selected
level.
IN FIFOOUT FIFO
00 FIFO 25% emptyFIFO 25% full
01 FIFO 50% emptyFIFO 50% full
10 FIFO 75% emptyFIFO 75% full
11 FIFO emptyFIFO full