Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-34
Freescale Semiconductor
13.5.22 Clock Select Register (PCSR)
All bits in this register are read/write and are cleared on hardware or software reset.
for certain restrictions on the use of the clock generation block.
15
14
8
7
6
5
3
2
0
Field NBP
—
CKI
FDIV
CMULT
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x39E
Figure 13-34. Clock Select Register (PCSR)
Table 13-17. PCSR Field Descriptions
Bits
Name
Description
15
NBP
Non-bypass mode select for the clock generation module.
0 The clock generation module is bypassed. Gen_FSC and GDCL are connected to FSC0 and
DCL0.
1 Selects non-bypassed mode. Gen_FSC and GDCL are synthesized from the incoming FSC0
or DCL0.
14–8
—
Reserved, should be cleared.
7–6
CKI
Clock select Input. Selects the source clock for the clock generation block.
00 DCL0
01 FSC0
1x Reserved
5–3
FDIV
FSC divide. Sets the divide ratio between GDCL and Gen_FSC.
000 ÷4
001 ÷8
010 ÷16
011 ÷32
100 ÷64
101 ÷128
110 ÷192
111 ÷256
2–0
CMULT
Clock multiplication ratio. Sets the ratio of the reference clock frequency to the GDCL frequency.
000 x 2
001 x 4
010 x 8
011 x 16
100 x 32
101 x 64
110 x 128
111 x 256