Electrical Characteristics
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
23-25
Figure 23-18. IDL Slave Timing
Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3
Name
Characteristic
Min
Max
Unit
P30
FSC input high before the falling edge of DCL0, DCL1 (setup time)
25
—
nS
P31
FSC0 input low before the rising edge of DCL0 (deassertion setup time),
FSC1 input low before the rising edge of DCL1 (deassertion setup time)
25
nS
P32
FSC0 input high after the falling edge of DCL0 (hold time),
FSC1 input high after the falling edge of DCL1 (hold time)
25
—
nS
P33
DCL0, DCL1 clock frequency
—
8192
KHz
P34
DCL0, DCL1 pulse-width low
45
55
% of DCL period
P35
DCL0, DCL1 pulse-width high
45
55
% of DCL period
P38
Delay from rising edge of FSC0 to low-z and valid data on DOUT0
Delay from rising edge of FSC1 to low-z and valid data on DOUT1
Delay from rising edge of DFSC2 to low-z and valid data on DOUT1
Delay from rising edge of DFSC3 to low-z and valid data on DOUT1, DOUT3
—30
nS
P39
Delay from rising edge of DCL0 to data valid on DOUT0,
Delay from rising edge of DCL1 to data valid on DOUT1, DOUT3
—30
nS
P40
Delay from rising edge of DCL0 to high-z on DOUT0,
Delay from rising edge of DCL1 to high-Z on DOUT1, DOUT3
—30
nS
P41
Data valid on DIN0 before rising edge of DCL0,
Data valid on DIN1 or DIN3 before rising edge of DCL1
25
—
nS
P42
Data valid on DIN0 after rising edge of DCL0,
Data valid on DIN1 or DIN3 after rising edge of DCL1
25
—
nS
DFSC[2:3]
DCL[0:1]
FSR[0,1]
P14
P19
P18
P16
P15
P17
P20
P21
P22
P23
P24
P26
P25
DOUT[0,1,3]
DIN[0:3]