System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
6-4
Freescale Semiconductor
determine if an internal peripheral is being accessed. MBAR masks specific address spaces using the
address space fields. Attempts to access a masked address space generate an external bus access.
Addresses hitting overlapping memory spaces take the following priority:
1. SRAM, ROM, and cache
2. MBAR
3. Chip select
Thus, if an overlapping address hits in the SRAM, ROM, or cache, the SIM will not generate a bus cycle,
either externally or to an on-chip peripheral.
NOTE
The MBAR region must be mapped to non-cacheable space.
The following example shows how to set the MBAR to location 0x1000_0000 using the D0 register.
Setting MBAR[V] validates the MBAR location. This example assumes all accesses are valid:
move.1 #0x10000001,DO
movec DO,MBAR
31
16 15
5
4
3
2
1
0
Field
BA
—
SC SD UC UD V
Reset
Undefined
0
R/W
W initially through MOVEC; R/W after initialization in supervisor mode
Address
CPU + 0x0C0F initially; MBAR+0x000 after initialization
Figure 6-2. Module Base Address Register (MBAR)
Table 6-2. MBAR Field Descriptions
Bits
Field
Description
31–16
BA
Base address. Defines the base address for a 64-Kbyte address range
.
15–5
—
Reserved, should be cleared.
4
SC
Setting masks supervisor code space in MBAR address range
3
SD
Setting masks supervisor data space in MBAR address range
2
UC
Setting masks user code space in MBAR address range
1
UD
Setting masks user data space in MBAR address range
0
V
Valid. Determines whether MBAR settings are valid.
0 MBAR contents are invalid.
1 MBAR contents are valid.
Attribute Mask Bits