IEEE 1149.1 Test Access Port (JTAG)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
21-2
Freescale Semiconductor
NOTE
Precautions to ensure that the IEEE 1149.1 test logic does not interfere with
Figure 21-1 shows the MCF5272 implementation of IEEE 1149.1.
Figure 21-1. Test Access Port Block Diagram
21.2
JTAG Test Access Port and BDM Debug Port
The JTAG test interface shares pins with the debug modules (see
Table 21-1).Table 21-1. JTAG Signals
Signal
Description
TCK/
PSTCLK
Test clock. TCK is the dedicated JTAG test logic clock input, independent of the CPU system clock. It provides a
clock for on-board test logic defined by the IEEE 1149.1 standard. TCK should be grounded if the JTAG port is not
used and MTMOD is tied low.
TMS/
BKPT
Test mode select. This input controls test mode operations for on-board test logic defined by the IEEE 1149.1
standard. Connecting TMS to VDD disables the test controller, making all JTAG circuits transparent to the system.
TDO/
DSO
Test and debug data out. Output for shifting data out of serial data port logic. Shifting out data depends on the state
of the JTAG controller state machine and the instructions in the instruction register. The shift occurs on the falling
edge of TCK. When not outputting data, TDO is placed in high-impedance state. TDO can also be three-stated to
allow bused or parallel connections to other devices having JTAG test access ports.
Decoder
4-Bit Instruction Register
ID (32 bits)
Boundary-Scan Register
Test Data Register
TAP
Controller
Bypass
(1 Bit)
TDC
TDI
TMS
TCK
30