Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-21
Table 13-4. P0ICR–P3ICR Field Descriptions
Bits
Name
Description
15
IE
Interrupt enable. Allows the port to generate interrupts to the CPU. When cleared, the IE bit masks all
periodic and aperiodic interrupts associated with the respective port.
14–12
—
Reserved, should be cleared.
11
GCR
Interrupt enable for the C/I channel receive.
0 Interrupt masked
1 Interrupt enabled. When set, an interrupt is enabled which occurs when the corresponding GCR
status bit is set.
10
GCT
C/I channel transmit Interrupt enable.
0 Interrupt masked
1 Interrupt enabled.
9
GMR
Interrupt enable for the monitor channel receive.
0 Interrupt masked
1 Interrupt enabled.
8
GMT
Interrupt enable for the monitor channel transmit.
0 Interrupt masked
1 Interrupt enabled.
7–6
—
Reserved, should be cleared.
5
DTIE
D transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[DTDE] or PnPSR[DTUE] is set.
4
B2TIE
B2 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2TDE] or PnPSR[B2TUE] is
set.
3
B1TIE
B1 transmit interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B1TDE] or PnPSR[B1TUE] is
set.
2
DRIE
D receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[DRDF] or PnPSR[DROE] is
set.
1
B2RIE
B2 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled. Interrupt occurs when the corresponding PnPSR[B2RDF] or PnPSR[B2ROE] is
set.
0
B1RIE
B1 receive interrupt enable.
0 Interrupt masked
1 Interrupt enabled.Interrupt occurs when the corresponding PnPSR[B1RDF] or PnPSR[B1ROE] is
set.