Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-16
Freescale Semiconductor
13.5.2
B2 Data Receive Registers (P0B2RR–P3B2RR)
All bits in these registers are read only and are set on hardware or software reset.
The PnB2RR registers contain the last four frames of data received on channel B2. (P0B2RR is the B2
channel data for port 0, P1B2RR is B2 for port 1, and so on.) The data are packed from LSB to MSB.
These registers are aligned on long-word boundaries from MBAR + 0x310 for P0B2RR to
frame and bit alignment within the 32-bit word.
13.5.3
D Data Receive Registers (P0DRR–P3DRR)
All bits in these registers are read-only and are set on hardware or software reset.
The PnDRR registers contain the last four frames of D-channel receive data packed from the least
significant bit, (lsb), to the most significant bit, (msb), for each of the four physical ports on the MCF5272.
P0DRR is the D-channel byte for port 0, P1DRR the D channel for port 1, and so on.
Each of the four byte-addressable registers, P0DRR-P3DRR, are packed to form one 32-bit register,
PnDRR, located at MBAR + 0x320. P0DRR is located in the MSB of the PnDRR register, P3DRR is
located in the LSB of the PnDRR register.
31
24
23
16
Field
Frame 0
Frame 1
Reset
1111_1111
R/W
Read Only
15
8
7
0
Field
Frame 2
Frame 3
Reset
1111_1111
R/W
Read Only
Addr
MBAR + 0x310 (P0B2RR); 0x314 (P1B2RR); 0x318 (P2B2RR); 0x31C (P3B2RR)
Figure 13-14. B2 Receive Data Registers P0B2RR – P3B2RR
31
24
23
16
Field
P0DRR
P1DRR
Reset
1111_1111
R/W
Read Only
15
8
7
0
Field
P2DRR
P3DRR
Reset
1111_1111
R/W
Read Only
Addr
MBAR + 0x320 (P0DRR); 0x321 (P1DRR); 0x322 (P2DRR); 0x323 (P3DRR)
Figure 13-15. D Receive Data Registers P0DRR–P3DRR