Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-4
Freescale Semiconductor
Figure 13-3 shows the shift register, shadow register, internal bus register, and multiplexor for each B
receive channel.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones.
Figure 13-3. GCI/IDL B-Channel Receive Data Register Demultiplexing
13.2.2
GCI/IDL B- and D-Channel Transmit Data Registers
Figure 13-4. GCI/IDL Transmit Data Flow
The maximum transmission rate for each GCI/IDL port is 144 Kbps: the sum of two 64-Kbps B channels
and one 16-Kbps D-channel. Frames of B1, B2, and D-channels are packed together in a similar way to the
receive side.
Because the reception and transmission of information on the GCI/IDL interface is deterministic, a
common interrupt is generated at the 2-KHz rate. It is expected that a common interrupt service routine
services the transmit and receive registers.
After reset, the B- and D-channel shift registers and shadow registers are initialized to all ones.
8 bits
DEMUX
32 bits
Internal Bus
8-KHz Rate
Shift Register (B1 or B2)
2-KHz transfer and interrupt
8 bits
Shadow Register
START
END
DIN
64 Kbps
32
B1, B2, Receive
Data Register
B1
B2
D
B1 Shift Register
B2 Shift Register
D Shift Register
Dout
DCL
32
8
Internal Bus
Multiplexing
Circuitry