Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
13-33
13.5.21 Sync Delay Registers (P0SDR–P3SDR)
All bits in these registers are read/write and are cleared on hardware or software reset.
The PnSDR registers contain the frame sync delay bits for each of the four ports on the MCF5272.
NOTE
If a sync delay value of 0 is specified, that is, PnSDR[SD] = 0x000, then the
programmable delay block is transparent. When bypassed, the input frame
sync passes directly to the output, making the frame-sync-width function
defined by PnSDR[FSW] unavailable.
The 8-bit frame-sync-width should not be confused with long frame sync
mode. The PLIC only supports short frame sync in IDL8 and IDL10 bit
modes for interfacing to external transceivers.
15
14
13
10
9
0
Field FSW1 FSW0
—
SD
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x394 (P0SDR); 0x396 (P1SDR); 0x398 (P2SDR); 0x39A (P3SDR)
Figure 13-33. Sync Delay Registers (P0SDR–P3SDR)
Table 13-16. P0SDR–P3SDR Field Descriptions
Bits
Name
Description
15–14
FSW[1–0]
Frame sync width. Sets the width, in clock cycles, of the output frame sync pulse.
00 Frame sync width = 1
01 Frame sync width = 2
10 Frame sync width = 8
11 Frame sync width = 16
13–10
—
Reserved, should be cleared.
9–0
SD
Sync delay. Range: 0–1023. Sets the delay, in DCL clock cycles, for DFSC3–DFSC0. The delay period
should be doubled in GCI mode because GCI has two clock cycles per data bit. See
Section 13.3, “PLIC