Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-6
Freescale Semiconductor
.
Figure 13-6. B-Channel Unencoded and HDLC Encoded Data
13.2.3.2
B-Channel HDLC Encoded Data
When the incoming B channels contain HDLC encoded data they are presented on the physical line least
significant bit (lsb) first. The Soft HDLC expects the first bit received to be aligned in the lsb position of
a byte, with the last bit received aligned in the msb position.
Because the presentation of HDLC encoded data on the physical interface is lsb (least significant bit) first
for B1 and B2 the lsb is right-aligned in the transmit and receive shift register, that is, the first bit of the
B-channel received is aligned in the lsb position through to the last received bit of a byte that is aligned in
the msb position.
The ordering of the bytes over four frames within the longword register is as for unencoded data; that is,
the first frame is aligned in the MSB through to the fourth frame, which is aligned in the LSB position. See
13.2.3.3
D-Channel HDLC Encoded Data
When the incoming D channels contain HDLC-encoded data, they are presented on the physical line lsb
first. The Soft HDLC expects the first bit received to be aligned in the lsb position of a byte, with the last
bit received aligned in the msb position.
DCL
FSR
Din/Dout
Frame 0
Frame 1
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
32-bit B1/B2 Receive/Transmit Registers, PnB1RR, PnB2RR, PnB1TR, PnB2TR
Frame 0
Frame 1
Frame 2
Frame 3
B7 B6 B5 B4 B3 B2 B1 B0 B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2
D0 D1
Din/Dout
B 1
B 2
D
B0 B1 B2 B3 B4 B5 B6 B7
B0 B1 B2 B3 B4 B5
D0 D1
B0 B1 B2 B3 B4 B5 B6 B7
Unencoded
HDLC
Encoded