List of Memory Maps
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
A-9
0x038C
Aperiodic Interrupt Status Register (PASR)
Reserved
Loop back Control (PLCR)
0x0392
Reserved
D Channel Request (PDRQR)
0x0394
Port0 Sync Delay (P0SDR)
Port1 Sync Delay (P1SDR)
0x0398
Port2 Sync Delay (P2SDR)
Port3 Sync Delay (P3SDR)
0x039C
Reserved
Clock Select (PCSR)
Table A-15. Ethernet Module Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0840
Ethernet Control Register (ECR)
0x0844
Ethernet Interrupt Event Register (EIR)
0x0848
Ethernet Interrupt Mask Register (EIMR)
0x084C
Ethernet Interrupt Vector Status (IVSR)
0x0850
Ethernet Rx Ring Updated Flag (RDAR)
0x0854
Ethernet Tx Ring Updated Flag (TDAR)
0x0880
Ethernet MII Data Register (MMFR)
0x0884
Ethernet MII Speed Register (MSCR)
0x08CC
Ethernet Receive Bound Register (FRBR)
0x08D0
Ethernet Rx FIFO Start Address (FRSR)
0x08E4
Transmit FIFO Watermark (TFWR)
0x08EC
Ethernet Tx FIFO Start Address (TFSR)
0x0944
Ethernet Rx Control Register (RCR)
0x0948
Maximum Frame Length Register (MFLR)
0x0984
Ethernet Tx Control Register (TCR)
0x0C00
Ethernet Address (Lower) (MALR)
0x0C04
Ethernet Address (Upper) (MAUR)
0x0C08
Ethernet Hash Table (Upper) (HTUR)
0x0C0C
Ethernet Hash Table (Lower) (HTLR)
0x0C10
Ethernet Rx Descriptor Ring (ERDSR)
0x0C14
Ethernet Tx Descriptor Rin (ETDSR)
0x0C18
Ethernet Rx Buffer Size (EMRBR)
0x0C40–
0x0DFF
FIFO RAM (EFIFO)
Table A-14. PLIC Module Memory Map (continued)
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]