List of Memory Maps
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
A-7
Table A-12. SDRAM Controller Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0180
Reserved
SDRAM Configuration Register (SDCR)
0x0184
Reserved
SDRAM Timing Register (SDTR)
Table A-13. Timer Module Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0200
Timer 0 Mode Register (TMR0)
Reserved
0x0204
Timer 0 Reference Register (TRR0)
Reserved
0x0208
Timer 0 Capture Register (TCAP0)
Reserved
0x020C
Timer 0 Counter Register (TCN0)
Reserved
0x0210
Timer 0 Event Register (TER0)
Reserved
0x0220
Timer 1 Mode Register (TMR1)
Reserved
0x0224
Timer 1 Reference Register (TRR1)
Reserved
0x0228
Timer 1 Capture Register (TCAP1)
Reserved
0x022C
Timer 1 Counter Register (TCN1)
Reserved
0x0230
Timer 1 Event Register (TER1)
Reserved
0x0240
Timer 2 Mode Register (TMR2)
Reserved
0x0244
Timer 2 Reference Register (TRR2)
Reserved
0x0248
Timer 2 Capture Register (TCAP2)
Reserved
0x024C
Timer 2 Counter Register (TCN2)
Reserved
0x0250
Timer 2 Event Register (TER2)
Reserved
0x0260
Timer 3 Mode Register (TMR3)
Reserved
0x0264
Timer 3 Reference Register (TRR3)
Reserved
0x0268
Timer 3 Capture Register (TCAP3)
Reserved
0x026C
Timer 3 Counter Register (TCN3)
Reserved
0x0270
Timer 3 Event Register (TER3)
Reserved
0x0280
Watchdog Reset Reference Register (WRRR)
Reserved
0x0284
Watchdog Interrupt Reference Register (WIRR)
Reserved
0x0288
Watchdog Counter Register (WCR)
Reserved
0x028C
Watchdog Event Register (WER)
Reserved