Universal Serial Bus (USB)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
12-26
Freescale Semiconductor
12.3.2.17 USB Endpoint 1–7 Interrupt Mask Registers (EPnIMR)
Figure 12-20 shows the USB endpoint 1–7 interrupt mask register.
Figure 12-20. USB Endpoint 1-7 Interrupt Mask Registers (EP
nIMR)
Table 12-16 lists field descriptions for the USB endpoint 1–7 interrupt mask register.
1
HALT
Endpoint halt interrupt. Set when the endpoint n HALT_ST bit is set.
0 No interrupt pending
1 Endpoint n halted
0
FIFO_LVL
FIFO threshold level reached interrupt. Indicates that the FIFO level has risen above or fallen below
the level set in the EPCTLn register for OUT or IN endpoints, respectively.
0 No interrupt pending
1 FIFO threshold level reached
15
5
4
3
2
1
0
Field
—
EOT_EN EOP_EN UNHALT_EN HALT_EN FIFO_LVL_EN
Reset
0000_0000_0000_0000
R/W
Addr
MBAR + 0x1092, 0x1096, 0x109A, 0x109E, 0x10A2, 0x10A6, 0x10AA
Table 12-16. EP
nIMR Field Descriptions
Bits
Name
Description
15–5
—
Reserved, should be cleared.
4–0
Interrupt mask. These bits are set when the user wants to activate the interrupt source for the specific bit.
Refer to
Table 12-15 for a description of each interrupt source.
1 Interrupt Enabled
0 Interrupt Disabled
Table 12-15. EPnISR Field Descriptions (continued)
Bits
Name
Description