Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
Freescale Semiconductor
19-27
can be enabled, the INT1 interrupt can be disabled, and USB power-down modes can be enabled along
with its interrupt. Then when the ISDN transceiver is activated, its interrupt request can generate the USB
wake on ring signal, which causes the host controller on the PC to initiate USB traffic to the device. This
in turn causes the USB module to wake up the CPU. Note that USB_WOR, when configured by setting
USBEPCTL0[WOR_EN], is level-sensitive.
19.12 Timer Module Signals
This section describes timer module signals.
19.12.1 Timer Input 0 (TIN0)
The timer input (TIN0) can be programmed to cause events to occur in timer counter 1. It can either clock
the event counter or provide a trigger to the timer value capture logic.
19.12.2 Timer Output (TOUT0)/PB7
Timer mode: Timer output (TOUT0) is the output from timer 0.
Port B mode: This pin can also be configured as I/O pin PB7.
19.12.3 Timer Input 1 (TIN1)/PWM Mode Output 2 (PWM_OUT2)
Timer mode: Timer input 1 (TIN1) can be programmed as an input that causes events to occur in timer
counter 2. This can either clock the event counter or provide a trigger to the timer value capture logic.
PWM mode: Pulse-width modulator 2 (PWM_OUT2) compare output.
19.12.4 Timer Output 1 (TOUT1)/PWM Mode Output 1 (PWM_OUT1)
Timer mode: Timer output (TOUT1) is the output from timer 1.
PWM mode: Pulse-width modulator 1 (PWM_OUT1) compare output.
19.13 Ethernet Module Signals
The following signals are used by the Ethernet module for data and clock signals.
These signals are multiplexed with the parallel port B PB15–PB8 signals.
19.13.1 Transmit Clock (E_TxCLK)
This is an input clock which provides a timing reference for E_TxEN, E_TxD[3:0] and E_TxER.