Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-18
Freescale Semiconductor
13.5.6
D Data Transmit Registers (P0DTR–P3DTR)
All bits in these registers are read/write and are set on hardware or software reset.
The PLTD registers contain four frames of D-channel transmit data, packed from lsb to msb, for each of
the four physical ports on the MCF5272. P0DTR is the D-channel byte for port 0, P1DTR the D channel
for port 1, and so on.
The four byte-addressable 8-bit registers, P0DTR–P3DTR, are packed to form one 32-bit register, PLTD.
PLTD is aligned on a long-word boundary at MBAR + 0x348 and can be read as a single 32-bit register.
P0DTR is located in the MSB of the PLTD register, P3DTR is located in the LSB of the PLTD register.
13.5.7
Port Configuration Registers (P0CR–P3CR)
PnCR are registers containing configuration information for each of the four ports on the MCF5272.
All bits in these registers are read/write and are cleared on hardware or software reset.
31
24
23
16
Field
P0DTR
P1DTR
Reset
1111_1111
R/W
Read/Write
15
8
7
0
Field
P2DTR
P3DTR
Reset
1111_1111
R/W
Read/Write
Addr
MBAR + 0x348 (P0DTR); 0x349 (P1DTR); 0x34A (P2DTR); 0x34B (P3DTR)
Figure 13-18. D Transmit Data Registers P0DTR–P3DTR
15
14
12
11
10
9
8
7
6
5
4
3
2
1
0
P0CR ON/OFF
M
—
G/S
—
ACT
—
SHB2 SHB1 ENB2
ENB1
P1CR ON/OFF
—
M
M/S
G/S
FSM ACT
—
SHB2 SHB1 ENB2
ENB1
P2CR ON/OFF
—
————
—
SHB2 SHB1 ENB2
ENB1
P3CR ON/OFF
—
DMX
—
SHB2 SHB1 ENB2
ENB1
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x350 (P0CR); 0x352 (P1CR); 0x354 (P2CR); 0x356 (P3CR)
Figure 13-19. Port Configuration Registers (P0CR–P3CR)