Signal Descriptions
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
19-12
Freescale Semiconductor
B12
A1
SDA0
—
A1/SDA0
A1/SDRAM-16bit A0
O
B13
A5
SDA4
SDA3
—
A5/SDA4/SDA3
A5/SDRAM-16bit
A4/SDRAM-32bit A3
O
B14
A6
SDA5
SDA4
—
A6/SDA5/SDA4
A6/SDRAM-16bit
A5/SDRAM-32bit A4
O
C1
PST2
—
PST2
Internal processor status
2
O
C2
PST1
—
PST1
Internal processor status
1
O
C3
DDATA0
—
DDATA0
Debug data 0
O
C4
TCK
PSTCLK
—
TCK/PSTCLK
JTAG test clock in/
BDM PSTCLK output
I/O
C5
A21
—
A21
O
C6
A18
—
A18
O
C7
D19
D3
—
D19/D3
I/O
C8
BS1
—
BS1
Byte strobe 1
O
C9
CAS0
—
CAS0
SDRAM column select
strobe
O
C10
A14
SDA13
SDA12
—
A14/SDA13/SDA12
A14/SDRAM-16bit
A13/SDRAM-32bit A12
O
C11
A11
—
SDA9
—
A11/SDA9
A11/SDRAM-32bit A9
O
C12
A7
SDA6
SDA5
—
A7/SDA6/SDA5
A7/SDRAM-16bit
A6/SDRAM-32bit A5
O
C13
A8
SDA7
SDA6
—
A8/SDA7/SDA6
A8/SDRAM-16bit
A7/SDRAM-32bit A6
O
C14
A9
SDA8
SDA7
—
A9/SDA8/SDA7
A9/SDRAM-16bit
A8/SDRAM-32bit A7
O
D1
PA1
USB_RP
—
PA1/USB_RP
Port A bit 1/
USB Rx positive
I/O
D2
PA0
USB_TP
—
PA0/USB_TP
Port A bit 0/
USB Tx positive
I/O
D3
PST3
—
PST3
Internal processor
status 3
O
D4
TRST
DSCLK
—
TRST/DSCLK
JTAG reset/BDM clock
I
D5
TDO
DSO
—
TDO/DSO
JTAG test data out
/BDM data out
O
D6
A19
—
A19
O
D7
A17
—
A17
O
Table 19-2. Signal Name and Description by Pin Number (Sheet 2 of 8)
Map
BGA
Pin
Pin Functions
Name
Description
I/O
0 (Reset)
1
2
3