System Integration Module (SIM)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
6-2
Freescale Semiconductor
The following is a list of the key SIM features:
Module base address register (MBAR)
— Base address location of all internal peripherals, SIM resources, and memory-mapped registers
— Address space masking to internal peripherals and SIM resources
Interrupt controller
— Programmable interrupt level (1–7) for internal peripheral interrupts
— Up to six external interrupt request inputs
Chip select module
— Eight dedicated programmable chip selects
— Address masking for memory block sizes from 4 Kbytes to 2 Gbytes
— Programmable wait states and port sizes
— Programmable address setup
— Programmable address hold for read and write
— SDRAM controller interface supported with CS7/SDCS
System protection
Power management
— Individual control for each on-chip peripheral
— Choice of low-power modes
Bus arbitration
— Configure arbitration for internal bus among ColdFire core, Ethernet controller, and DMA
6.2
Programming Model
The following sections describe the registers incorporated into the SIM.
6.2.1
SIM Register Memory Map
Table 6-1 shows the memory map for the SIM registers. The internal registers in the SIM are
memory-mapped registers offset from the MBAR address pointer defined in MBAR[BA]. This
SIM registers depend on the base address defined in MBAR[BA], MBAR must be programmed before
SIM registers can be accessed.