List of Memory Maps
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
A-2
Freescale Semiconductor
NOTE
MBAR must only be written using the MOVEC instruction. Writing to
address MBAR+0x0000 causes unpredictable device operation.
Table A-2. CPU Space Registers Memory Map
CPU SPACE
ADDRESS
NAME
Size
SYSTEM CONFIGURATION REGISTERS
Program Access
Debug Access
0x0002
(CACR)
32
Cache Control Register
MOVEC
RCREG, WCREG
0x0004
(ACR0)
32
Cache Access Control Register 0
MOVEC
RCREG, WCREG
0x0005
(ACR1)
32
Cache Access Control Register 1
MOVEC
RCREG, WCREG
0x008x
A7:A0
32
Address registers A7:A0
MOVE
RAREG, WAREG
0x008x
D7:D0
32
Data registers D7:D0
MOVE
RDREG, WDREG
0x0801
(VBR)
32
Vector Base Register
MOVEC
RCREG, WCREG
0x080E
CCR
8
Condition Code Register (Debug only)
MOVE to/from CCR
RCREG, WCREG
0x080F
PC
32
Program Counter (Debug only)
RCREG, WCREG
0x0C00
ROMBAR
32
ROM Base Address Register
MOVEC
RCREG, WCREG
0x0C04
RAMBAR
32
SRAM Base Address Register
MOVEC
RCREG, WCREG
0x0C0F
MBAR
32
Module Base Address Register
MOVEC
Table A-3. On-Chip Peripherals and Configuration Registers Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0000
Module Base Address Register, Read Only (MBAR)
0x0004
System Configuration Register (SCR)
Reserved
0x0006
Reserved
System Protection Register (SPR)
0x0008
Power Management Register (PMR)
0x000E
Reserved
Activate Low Power Register (ALPR)
0x0010
Device Identification Register (DIR)
Table A-4. Interrupt Control Register Memory Map
MBAR
Offset
[31:24]
[23:16]
[15:8]
[7:0]
0x0020
Interrupt Control Register 1 (ICR1)
0x0024
Interrupt Control Register 2 (ICR2)
0x0028
Interrupt Control Register 3 (ICR3)
0x002C
Interrupt Control Register 4 (ICR4)
0x0030
Interrupt Source Register (ISR)
0x0034
Programmable Interrupt Transition Register (PITR)
0x0038
Programmable Interrupt Wakeup Register (PIWR)
0x003F
Reserved
Programmable Interrupt
Vector Register (PIVR)