Physical Layer Interface Controller (PLIC)
MCF5272 ColdFire Integrated Microprocessor User’s Manual, Rev. 3
13-28
Freescale Semiconductor
13.5.16 GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
All bits in these registers are read only and are cleared on hardware or software reset.
The PnGCIR registers contain the received C/I bits for one of each of the four ports on the MCF5272.
31
29
28
27
26
25
24
23
21
20
19
18
17
16
Field
—
F
C3C2C1
C0
—
F
C3
C2C1
C0
Chan
P0GCIR
P1GCIR
Reset
0000_0000_0000_0000
R/W
Read Only
15
13
12
11
10
9
8
7
5
4
3
2
1
0
Field
—
F
C3C2C1
C0
—
F
C3
C2C1
C0
Chan
P2GCIR
P3GCIR
Reset
0000_0000_0000_0000
R/W
Read Only
Addr
MBAR + 0x374 (P0GCIR), 0x375 (P1GCIR), 0x376 (P2GCIR), 0x377 (P3GCIR)
Figure 13-28. GCI C/I Channel Receive Registers (P0GCIR–P3GCIR)
Table 13-11. P0GCIR–P3GCIR Field Descriptions
Bits
Name
Description
31–29, 23–21,
15–13, 7–5
—
Reserved, should be cleared.
28, 20, 12, 4
F
Full. This bit is set by the C/I channel controller to indicate to the CPU that new C/I channel data
has been received and is available for processing. It is automatically cleared by a CPU read. The
clearing of this bit by reading this register also clears the aperiodic GCR interrupt.
27–24, 19–16,
11–8, 3–0
C3–C0
C/I bits. These four bits are received on the GCI or SCIT channel 0. When a change in the C/I data
value is received in two successive frames, it is interpreted as being valid and is passed on to the
CPU, via this register. A maskable interrupt is generated when data is written into any of the four
available positions.